signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
type STATE_PC is (IDLE, FETCH, FORWARD, UART_DONE, CR, CR_WAIT,
signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
type STATE_PC is (IDLE, FETCH, FORWARD, UART_DONE, CR, CR_WAIT,