pc-com: zeilennummer auch ausgeben

[hwmod.git] / src / pc_communication.vhd

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index ca885dd5da144295b812c08b926f015af20323c0..410bc4fbb05aa0674f9e0eab1aa024bfa3da3b4d 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -37,7 +37,10 @@ architecture beh of pc_communication is
        signal tx_done_i, tx_done_i_next : std_logic;
        signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
 
-       type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT, NL, NL_WAIT);
+       type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT,
+               NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
+               PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
+               PRINT_NO5_WAIT, PRINT_NO6, PRINT_NO0_WAIT);
        signal state, state_next : STATE_PC ;
 begin
        pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
@@ -69,7 +72,8 @@ begin
        end process sync;
 
        process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
-               pc_done)
+                       pc_done)
+               variable tmp : std_logic_vector(6 downto 0);
        begin
                get_next <= '0';
                new_i_next <= '0';
@@ -82,15 +86,76 @@ begin
                        when IDLE =>
 --                             if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
                                if (rx_new = '1') or btn_a = '0' then
+                                       state_next <= PRINT_NO0_WAIT;
+                               end if;
+
+                       when PRINT_NO0_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO1;
+                               end if;
+                       when PRINT_NO1 =>
+                               tx_data_i_next <= x"28"; -- '('
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= PRINT_NO1_WAIT;
+                               end if;
+                       when PRINT_NO1_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO2;
+                               end if;
+                       when PRINT_NO2 =>
+                               tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= PRINT_NO2_WAIT;
+                               end if;
+                       when PRINT_NO2_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO3;
+                               end if;
+                       when PRINT_NO3 =>
+                               tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= PRINT_NO3_WAIT;
+                               end if;
+                       when PRINT_NO3_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO4;
+                               end if;
+                       when PRINT_NO4 =>
+                               tx_data_i_next <= x"29"; -- ')'
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= PRINT_NO4_WAIT;
+                               end if;
+                       when PRINT_NO4_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO5;
+                               end if;
+                       when PRINT_NO5 =>
+                               tx_data_i_next <= x"24"; -- '$'
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= PRINT_NO5_WAIT;
+                               end if;
+                       when PRINT_NO5_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO6;
+                               end if;
+                       when PRINT_NO6 =>
+                               tx_data_i_next <= x"20"; -- ' '
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
                                        state_next <= FETCH;
                                end if;
+
                        when FETCH =>
                                get_next <= '1';
                                if pc_done = '1' and tx_done_i = '0' then
+                                       state_next <= FORWARD;
                                        if pc_char = x"00" then
                                                state_next <= UART_DONE;
-                                       else
-                                               state_next <= FORWARD;
                                        end if;
                                end if;
                        when FORWARD =>
@@ -105,7 +170,7 @@ begin
                                if tx_done_i = '1' then
                                        state_next <= UART_DONE;
                                end if;
-                       when UART_DONE => null;
+                       when UART_DONE =>
                                state_next <= FETCH;
                                spalte_next <= spalte + 1;
                                if spalte = HSPALTE_MAX + 1 then
@@ -128,7 +193,14 @@ begin
                                        state_next <= CR_WAIT;
                                end if;
                        when CR_WAIT =>
-                               state_next <= FETCH;
+                               tmp := std_logic_vector(to_unsigned(zeile,7));
+                               if tmp(0) = '0' then
+                                       -- es handelt sich um eingabe
+                                       -- => print zeilennummer
+                                       state_next <= PRINT_NO0_WAIT;
+                               else
+                                       state_next <= FETCH;
+                               end if;
                                if zeile = HZEILE_MAX then
                                        state_next <= IDLE;
                                        zeile_next <= 0;