spartan3e: rx_test

[hwmod.git] / src / calc_s3e.vhd

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index 09a2c941d38a096f504fbc07a3059fc5fafc577a..e5f956e50ac5580bba62e6e4702abfa15df5df7f 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -15,7 +15,7 @@ entity calc is
                -- btnA
                -- TODO: pins
                -- rs232
-               --rxd : in std_logic;
+               rxd : in std_logic;
                txd : out std_logic;
                -- vga
                vsync_n : out std_logic;
@@ -63,12 +63,12 @@ architecture top of calc is
        -- parser/scanner
        signal do_it, finished : std_logic;
        -- rs232
-       --signal rx_new, rxd_sync : std_logic;
-       --signal rx_data : std_logic_vector (7 downto 0);
+       signal rx_new, rxd_sync : std_logic;
+       signal rx_data : std_logic_vector (7 downto 0);
        signal tx_new, tx_done : std_logic;
        signal tx_data : std_logic_vector (7 downto 0);
 begin
-       led0 <= '0';
+       led0 <= rxd_sync;
        led1 <= '1';
        sys_res_n <= not sys_res;
 
@@ -186,7 +186,10 @@ begin
                finished => finished,
                -- test: uart_tx
                tx_data => tx_data,
-               tx_new => tx_new
+               tx_new => tx_new,
+               -- test: uart_rx
+               rx_data => rx_data,
+               rx_new => rx_new
        );
 
        -- ps/2
@@ -206,31 +209,31 @@ begin
        );
 
        -- synchronizer fuer rxd
-       --sync_rxd_inst : entity work.sync(beh)
-       --generic map (
-       --      SYNC_STAGES => 2,
-       --      RESET_VALUE => '1'
---     )
-       --port map (
-       --      sys_clk => CLK_50MHZ,
-       --      sys_res_n => sys_res_n,
-       --      data_in => rxd,
-       --      data_out => rxd_sync
-       --);
+       sync_rxd_inst : entity work.sync(beh)
+       generic map (
+               SYNC_STAGES => 2,
+               RESET_VALUE => '1'
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               data_in => rxd,
+               data_out => rxd_sync
+       );
 
        -- rs232-rx
-       --rs232rx_inst : entity work.uart_rx(beh)
-       --generic map (
-       --      CLK_FREQ => 50000000,
-       --      BAUDRATE => 115200
-       --)
-       --port map (
-       --      sys_clk => CLK_50MHZ,
-       --      sys_res_n => sys_res_n,
-       --      rxd => rxd_sync,
-       --      rx_data => rx_data,
-       --      rx_new => rx_new
-       --);
+       rs232rx_inst : entity work.uart_rx(beh)
+       generic map (
+               CLK_FREQ => 50000000,
+               BAUDRATE => 115200
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               rxd => rxd_sync,
+               rx_data => rx_data,
+               rx_new => rx_new
+       );
 
        -- rs232-tx
        rs232tx_inst : entity work.uart_tx(beh)