signal do_it, finished : std_logic;
-- debouncing
signal sys_res_n_sync : std_logic;
+ signal btn_a_sync : std_logic;
-- rs232
signal rx_new, rxd_sync : std_logic;
signal rx_data : std_logic_vector (7 downto 0);
signal tx_new, tx_done : std_logic;
signal tx_data : std_logic_vector (7 downto 0);
-
- signal btn_a_sync : std_logic;
-
begin
-- vga/ipcore
textmode_vga_inst : entity work.textmode_vga(struct)
pc_char => pc_char,
pc_busy => pc_busy,
pc_done => pc_done
-
);
-- parser
)
port map (
sys_clk => sys_clk,
- sys_res_n => '1',
+ sys_res_n => sys_res_n_sync,
data_in => btn_a,
data_out => btn_a_sync
);