tx-test: transmit erfolgreich getestet :)

[hwmod.git] / src / calc.vhd

diff --git a/src/calc.vhd b/src/calc.vhd
index bd4e903f80c51dd859479a9dd96270054c6309a0..3c9031798464eaea45e4b9dfd5384dc5d0a569ee 100644 (file)
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -16,7 +16,7 @@ entity calc is
                -- btnA
                -- TODO: pins
                -- rs232
-               rxd : in std_logic;
+               --rxd : in std_logic;
                txd : out std_logic;
                -- vga
                vsync_n : out std_logic;
@@ -61,11 +61,10 @@ architecture top of calc is
        -- debouncing
        signal sys_res_n_sync : std_logic;
        -- rs232
-       signal rx_new, rxd_sync : std_logic;
-       signal rx_data : std_logic_vector (7 downto 0);
+       --signal rx_new, rxd_sync : std_logic;
+       --signal rx_data : std_logic_vector (7 downto 0);
        signal tx_new, tx_done : std_logic;
        signal tx_data : std_logic_vector (7 downto 0);
-       signal txd_out : std_logic;
 begin
        -- vga/ipcore
        textmode_vga_inst : entity work.textmode_vga(struct)
@@ -178,7 +177,10 @@ begin
                s_backspace => s_backspace,
                -- parser
                do_it => do_it,
-               finished => finished
+               finished => finished,
+               -- test: uart_tx
+               tx_data => tx_data,
+               tx_new => tx_new
        );
 
        -- ps/2
@@ -213,31 +215,31 @@ begin
        );
 
        -- synchronizer fuer rxd
-       sync_rxd_inst : entity work.sync(beh)
-       generic map (
-               SYNC_STAGES => 2,
-               RESET_VALUE => '1'
-       )
-       port map (
-               sys_clk => sys_clk,
-               sys_res_n => sys_res_n_sync,
-               data_in => rxd,
-               data_out => rxd_sync
-       );
+       --sync_rxd_inst : entity work.sync(beh)
+       --generic map (
+       --      SYNC_STAGES => 2,
+       --      RESET_VALUE => '1'
+--     )
+       --port map (
+       --      sys_clk => sys_clk,
+       --      sys_res_n => sys_res_n_sync,
+       --      data_in => rxd,
+       --      data_out => rxd_sync
+       --);
 
        -- rs232-rx
-       rs232rx_inst : entity work.uart_rx(beh)
-       generic map (
-               CLK_FREQ => 33330000,
-               BAUDRATE => 115200
-       )
-       port map (
-               sys_clk => sys_clk,
-               sys_res_n => sys_res_n_sync,
-               rxd => rxd_sync,
-               rx_data => rx_data,
-               rx_new => rx_new
-       );
+       --rs232rx_inst : entity work.uart_rx(beh)
+       --generic map (
+       --      CLK_FREQ => 33330000,
+       --      BAUDRATE => 115200
+       --)
+       --port map (
+       --      sys_clk => sys_clk,
+       --      sys_res_n => sys_res_n_sync,
+       --      rxd => rxd_sync,
+       --      rx_data => rx_data,
+       --      rx_new => rx_new
+       --);
 
        -- rs232-tx
        rs232tx_inst : entity work.uart_tx(beh)
@@ -248,7 +250,7 @@ begin
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
-               txd => txd_out,
+               txd => txd,
                tx_data => tx_data,
                tx_new => tx_new,
                tx_done => tx_done