allgemein: components fuer die module

[hwmod.git] / src / calc.vhd

diff --git a/src/calc.vhd b/src/calc.vhd
index b967e1fce429a703ebdcba03e86aaa934fe7b86e..20d2027e62013e409327ac531a1f4792612e3207 100644 (file)
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -31,6 +31,8 @@ entity calc is
 end entity calc;
 
 architecture top of calc is
+       constant CLK_FREQ : integer := 33000000;
+       constant BAUDRATE : integer := 115200;
        -- ps/2
        signal new_data : std_logic;
        signal data : std_logic_vector(7 downto 0);
@@ -74,7 +76,7 @@ architecture top of calc is
        signal tx_data : std_logic_vector (7 downto 0);
 begin
        -- vga/ipcore
-       textmode_vga_inst : entity work.textmode_vga(struct)
+       textmode_vga_inst : textmode_vga
        generic map (
                VGA_CLK_FREQ => 25000000,
                BLINK_INTERVAL_MS => 500,
@@ -96,14 +98,14 @@ begin
        );
 
        -- pll fuer vga
-       vpll_inst : entity work.vpll(syn)
+       vpll_inst : vpll
        port map (
                inclk0 => sys_clk,
                c0 => vga_clk
        );
 
        -- display
-       display_inst : entity work.display(beh)
+       display_inst : display
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n_sync,
@@ -123,7 +125,7 @@ begin
        );
 
        -- history
-       history_inst : entity work.history(beh)
+       history_inst : history
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n_sync,
@@ -158,7 +160,7 @@ begin
        );
 
        -- parser
-       parser_inst : entity work.parser(beh)
+       parser_inst : parser
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n_sync,
@@ -176,7 +178,7 @@ begin
        );
 
        -- scanner
-       scanner_inst : entity work.scanner(beh)
+       scanner_inst : scanner
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n_sync,
@@ -194,9 +196,9 @@ begin
        );
 
        -- ps/2
-       ps2_inst : entity work.ps2_keyboard_controller(beh)
+       ps2_inst : ps2_keyboard_controller
        generic map (
-               CLK_FREQ => 33330000,
+               CLK_FREQ => CLK_FREQ,
                SYNC_STAGES => 2
        )
        port map (
@@ -212,7 +214,7 @@ begin
        -- debouncer fuer sys_res_n
        sys_res_n_debounce_inst : debounce
        generic map (
-               CLK_FREQ => 33330000,
+               CLK_FREQ => CLK_FREQ,
                TIMEOUT => 1 ms,
                RESET_VALUE => '1',
                SYNC_STAGES => 2
@@ -225,7 +227,7 @@ begin
        );
 
        -- synchronizer fuer rxd
-       sync_rxd_inst : entity work.sync(beh)
+       sync_rxd_inst : sync
        generic map (
                SYNC_STAGES => 2,
                RESET_VALUE => '1'
@@ -240,7 +242,7 @@ begin
        -- debouncer fuer btn_a
        btn_a_debounce_inst : debounce
        generic map (
-               CLK_FREQ => 33330000,
+               CLK_FREQ => CLK_FREQ,
                TIMEOUT => 1 ms,
                RESET_VALUE => '1',
                SYNC_STAGES => 2
@@ -253,10 +255,10 @@ begin
        );
 
        -- rs232-rx
-       rs232rx_inst : entity work.uart_rx(beh)
+       rs232rx_inst : uart_rx
        generic map (
-               CLK_FREQ => 33330000,
-               BAUDRATE => 115200
+               CLK_FREQ => CLK_FREQ,
+               BAUDRATE => BAUDRATE
        )
        port map (
                sys_clk => sys_clk,
@@ -267,10 +269,10 @@ begin
        );
 
        -- rs232-tx
-       rs232tx_inst : entity work.uart_tx(beh)
+       rs232tx_inst : uart_tx
        generic map (
-               CLK_FREQ => 33330000,
-               BAUDRATE => 115200
+               CLK_FREQ => CLK_FREQ,
+               BAUDRATE => BAUDRATE
        )
        port map (
                sys_clk => sys_clk,
@@ -281,7 +283,7 @@ begin
                tx_done => tx_done
        );
 
-       pc_com_inst : entity work.pc_communication(beh)
+       pc_com_inst : pc_communication
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -303,4 +305,3 @@ begin
        );
 
 end architecture top;
-