allgemein: components fuer die module

[hwmod.git] / src / beh_uart_tx_tb.vhd

diff --git a/src/beh_uart_tx_tb.vhd b/src/beh_uart_tx_tb.vhd
index 3f75682e8b952fb00f49ff797a20b7339ae8f0a5..db4453c1828ff6a8ac1c43670fbab3b00a960843 100644 (file)
--- a/src/beh_uart_tx_tb.vhd
+++ b/src/beh_uart_tx_tb.vhd
@@ -15,7 +15,7 @@ architecture sim of beh_uart_tx_tb is
        signal tx_data : std_logic_vector (7 downto 0);
        signal stop : boolean := false;
 begin
-       inst : entity work.uart_tx(beh)
+       inst : uart_tx
        generic map (
                CLK_FREQ => CLK_FREQ,
                BAUDRATE => BAUDRATE