added initial uart_rx files, not exaustively tested though.

[hwmod.git] / src / beh_uart_rx_tb.vhd

diff --git a/src/beh_uart_rx_tb.vhd b/src/beh_uart_rx_tb.vhd
new file mode 100644 (file)
index 0000000..bca920a
--- /dev/null
+++ b/src/beh_uart_rx_tb.vhd
@@ -0,0 +1,57 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity beh_uart_rx_tb is
+end entity beh_uart_rx_tb;
+
+architecture sim of beh_uart_rx_tb is
+
+       constant clk_period : time := 2ns;
+       signal clock : std_logic;
+       signal reset : std_logic;
+       signal done : std_logic;
+       signal newsig : std_logic;
+       signal data : std_logic_vector(7 downto 0);
+       signal serial_in: std_logic;
+begin
+       inst : entity work.uart_rx(beh)
+       port map (
+               sys_clk => clock,
+               sys_res => reset,
+               txd => serial_in,
+               tx_data => data,
+               tx_new => newsig
+       );
+
+       stimuli : process
+       begin
+               serial_in <= '0';
+               wait for 10ns;
+               --send 'Hallo Welt'
+               serial_in <= '1';
+               wait for clk_period;
+               serial_in <= '0';
+               wait for 1000ns;
+
+               assert false report "Test finished" severity failure;
+       end process stimuli;
+
+       res_gen : process
+       begin
+               reset <= '0';
+               wait for 20ns;
+               reset <= '1';
+               wait for 1000ns;
+       end process res_gen;
+
+       clock_gen : process
+       begin
+               clock <= '0';
+               wait for clk_period/2;
+               clock <= '1';
+               wait for clk_period/2;
+       end process clock_gen;
+
+end sim;