pc-com: new line und carrige return

[hwmod.git] / src / beh_pc_communication_tb.vhd

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index d2a693e017c6c688626255cfd54c6d244cfb026f..d9f8789122d6d1d065b7f58d68f7223c12ccc474 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -23,7 +23,6 @@ architecture sim of beh_pc_communication_tb is
                signal rx_new : std_logic;
                signal pc_get : std_logic;
                signal pc_done : std_logic;
-               signal pc_busy : std_logic;
                signal rx_data, tx_data : std_logic_vector(7 downto 0);
 
                signal pc_zeile : hzeile;
@@ -53,7 +52,6 @@ begin
                pc_spalte => pc_spalte,
                pc_get => pc_get,
                pc_done => pc_done,
-               pc_busy => pc_busy,
                pc_char => pc_char
        );
 
@@ -75,7 +73,6 @@ begin
        begin
                pc_char <= (others => '0');
                pc_done <= '0';
-               pc_busy <= '0';
                wait until sys_res_n = '1';
 
                while not endfile (f) loop
@@ -87,11 +84,9 @@ begin
                                wait until rising_edge(pc_get);
                                wait for 150 ns;
                                pc_char <= (others => '0');
-                               pc_busy <= '1';
                                wait for 30 ns;
                                pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
                                i := i + 1;
-                               pc_busy <= '0';
                                pc_done <= '1';
                                wait for 30 ns;
                        end loop;