allgemein: components fuer die module

[hwmod.git] / src / beh_loopback_tb.vhd

diff --git a/src/beh_loopback_tb.vhd b/src/beh_loopback_tb.vhd
index 5e040f06b33fe4ed897fd34ebdba9cec7a30f509..4bc01c8a38e8b4fa965796ef33ba08aaba594da8 100644 (file)
--- a/src/beh_loopback_tb.vhd
+++ b/src/beh_loopback_tb.vhd
@@ -17,7 +17,7 @@ architecture sim of beh_loopback_tb is
        signal tx_data : std_logic_vector (7 downto 0);
        signal stop : boolean := false;
 begin
-       inst_rx : entity work.uart_rx(beh)
+       inst_rx : uart_rx
        generic map (
                CLK_FREQ => CLK_FREQ,
                BAUDRATE => BAUDRATE
@@ -29,7 +29,7 @@ begin
                rx_data => rx_data,
                rx_new => rx_new
        );
-       inst_tx : entity work.uart_tx(beh)
+       inst_tx : uart_tx
        generic map (
                CLK_FREQ => CLK_FREQ,
                BAUDRATE => BAUDRATE