allgemein: components fuer die module

[hwmod.git] / src / beh_alu_tb.vhd

diff --git a/src/beh_alu_tb.vhd b/src/beh_alu_tb.vhd
index f6c6d5b3918ed1620a30102c0013d286c371f3e1..96cbeebca2ea642cac93e36714a9a6068a4b88fb 100644 (file)
--- a/src/beh_alu_tb.vhd
+++ b/src/beh_alu_tb.vhd
@@ -12,9 +12,8 @@ architecture sim of beh_alu_tb is
        signal op1, op2, op3, opM : csigned;
        signal stop : boolean := false;
 begin
-       inst : entity work.alu(beh)
-       port map
-       (
+       inst : alu
+       port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
                do_calc => do_calc,