spartan3e: reset sollte man mindestens mit high verbinden - geht jetzt :)

[hwmod.git] / spartan3e / spartan3e.ucf

diff --git a/spartan3e/spartan3e.ucf b/spartan3e/spartan3e.ucf
index 64826bb17b23b1acd1230d2e5db158aad2257794..f87cd5543f4ee1e26730e430f7efda61f5354b8a 100644 (file)
--- a/spartan3e/spartan3e.ucf
+++ b/spartan3e/spartan3e.ucf
@@ -15,9 +15,9 @@
 #NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
 #NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
 # ==== Clock inputs (CLK) ====
-NET "sys_clk_real" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
+NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
 # Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
-NET "sys_clk_real" PERIOD = 20 ns HIGH 40 %;
+NET "CLK_50MHZ" PERIOD = 20 ns HIGH 40 %;
 #NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
 #NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
 # ==== Digital-to-Analog Converter (DAC) ====
@@ -274,6 +274,6 @@ NET "vsync_n" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
 #NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
 #NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 #NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "sys_clk_real" TNM_NET = "sys_clk_real";
+NET "CLK_50MHZ" TNM_NET = "CLK_50MHZ";
 #NET "clk_reg1" TNM_NET = "clk_reg1";
 #TIMESPEC "TS_clk_reg1" = PERIOD "clk_reg1" 40 ns HIGH 50 %;