projects / hwmod.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
one place for all my love
[hwmod.git] / demo / quartus / simulation / modelsim / demo_modelsim.xrf
diff --git a/demo/quartus/simulation/modelsim/demo_modelsim.xrf b/demo/quartus/simulation/modelsim/demo_modelsim.xrf
new file mode 100644 (file)
index 0000000..fd093b7
--- /dev/null
+++ b/demo/quartus/simulation/modelsim/demo_modelsim.xrf
@@ -0,0 +1,113 @@
+vendor_name = ModelSim
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_pkg.vhd
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf
+source_file = 1, /opt/quartus/libraries/megafunctions/altpll.tdf
+source_file = 1, /opt/quartus/libraries/megafunctions/aglobal70.inc
+source_file = 1, /opt/quartus/libraries/megafunctions/stratix_pll.inc
+source_file = 1, /opt/quartus/libraries/megafunctions/stratixii_pll.inc
+source_file = 1, /opt/quartus/libraries/megafunctions/cycloneii_pll.inc
+source_file = 1, /opt/quartus/libraries/megafunctions/cbx.lst
+source_file = 1, /opt/quartus/libraries/megafunctions/lpm_divide.tdf
+source_file = 1, /opt/quartus/libraries/megafunctions/abs_divider.inc
+source_file = 1, /opt/quartus/libraries/megafunctions/sign_div_unsign.inc
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/lpm_divide_85m.tdf
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/sign_div_unsign_fkh.tdf
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_lkc.tdf
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_mkc.tdf
+design_name = demo_top
+instance = comp, \inst|counter[3]~I\, inst|counter[3], demo_top, 1
+instance = comp, \inst|counter[6]~I\, inst|counter[6], demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25_I\, inst|Mod0|auto_generated|divider|divider|StageOut[54]~25, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26_I\, inst|Mod0|auto_generated|divider|divider|StageOut[53]~26, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27_I\, inst|Mod0|auto_generated|divider|divider|StageOut[52]~27, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21_I\, inst|Mod0|auto_generated|divider|divider|StageOut[50]~21, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22_I\, inst|Mod0|auto_generated|divider|divider|StageOut[49]~22, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638_I\, inst|Mod0|auto_generated|divider|divider|StageOut[59]~638, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641_I\, inst|Mod0|auto_generated|divider|divider|StageOut[62]~641, demo_top, 1
+instance = comp, \inst|ledstate_next~434_I\, inst|ledstate_next~434, demo_top, 1
+instance = comp, \inst|ledstate_next~435_I\, inst|ledstate_next~435, demo_top, 1
+instance = comp, \CLK~I\, CLK, demo_top, 1
+instance = comp, \inst1|altpll_component|pll\, inst1|altpll_component|pll, demo_top, 1
+instance = comp, \inst1|altpll_component|_clk0~clkctrl_I\, inst1|altpll_component|_clk0~clkctrl, demo_top, 1
+instance = comp, \inst|Add0~100_I\, inst|Add0~100, demo_top, 1
+instance = comp, \inst|Add0~102_I\, inst|Add0~102, demo_top, 1
+instance = comp, \inst|Add0~104_I\, inst|Add0~104, demo_top, 1
+instance = comp, \inst|Add0~106_I\, inst|Add0~106, demo_top, 1
+instance = comp, \inst|Add0~108_I\, inst|Add0~108, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31_I\, inst|Mod0|auto_generated|divider|divider|StageOut[48]~31, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23_I\, inst|Mod0|auto_generated|divider|divider|StageOut[48]~23, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18, demo_top, 1
+instance = comp, \inst|Add0~96_I\, inst|Add0~96, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17_I\, inst|Mod0|auto_generated|divider|divider|StageOut[54]~17, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18_I\, inst|Mod0|auto_generated|divider|divider|StageOut[53]~18, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19_I\, inst|Mod0|auto_generated|divider|divider|StageOut[52]~19, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29_I\, inst|Mod0|auto_generated|divider|divider|StageOut[50]~29, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636_I\, inst|Mod0|auto_generated|divider|divider|StageOut[57]~636, demo_top, 1
+instance = comp, \RESET~I\, RESET, demo_top, 1
+instance = comp, \inst|counter[1]~I\, inst|counter[1], demo_top, 1
+instance = comp, \inst|Add0~98_I\, inst|Add0~98, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30_I\, inst|Mod0|auto_generated|divider|divider|StageOut[49]~30, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639_I\, inst|Mod0|auto_generated|divider|divider|StageOut[58]~639, demo_top, 1
+instance = comp, \inst|counter[2]~I\, inst|counter[2], demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28_I\, inst|Mod0|auto_generated|divider|divider|StageOut[51]~28, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20_I\, inst|Mod0|auto_generated|divider|divider|StageOut[51]~20, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642_I\, inst|Mod0|auto_generated|divider|divider|StageOut[60]~642, demo_top, 1
+instance = comp, \inst|counter[4]~I\, inst|counter[4], demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640_I\, inst|Mod0|auto_generated|divider|divider|StageOut[61]~640, demo_top, 1
+instance = comp, \inst|counter[5]~I\, inst|counter[5], demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637_I\, inst|Mod0|auto_generated|divider|divider|StageOut[56]~637, demo_top, 1
+instance = comp, \inst|counter[0]~I\, inst|counter[0], demo_top, 1
+instance = comp, \inst|Equal1~58_I\, inst|Equal1~58, demo_top, 1
+instance = comp, \inst|Equal1~59_I\, inst|Equal1~59, demo_top, 1
+instance = comp, \inst|knightlight~1269_I\, inst|knightlight~1269, demo_top, 1
+instance = comp, \inst|knightlight~1270_I\, inst|knightlight~1270, demo_top, 1
+instance = comp, \inst|knightlight[4]~I\, inst|knightlight[4], demo_top, 1
+instance = comp, \inst|knightlight~1271_I\, inst|knightlight~1271, demo_top, 1
+instance = comp, \inst|knightlight~1272_I\, inst|knightlight~1272, demo_top, 1
+instance = comp, \inst|knightlight[3]~I\, inst|knightlight[3], demo_top, 1
+instance = comp, \inst|knightlight~1273_I\, inst|knightlight~1273, demo_top, 1
+instance = comp, \inst|knightlight~1274_I\, inst|knightlight~1274, demo_top, 1
+instance = comp, \inst|knightlight[2]~I\, inst|knightlight[2], demo_top, 1
+instance = comp, \inst|knightlight~1277_I\, inst|knightlight~1277, demo_top, 1
+instance = comp, \inst|knightlight[0]~I\, inst|knightlight[0], demo_top, 1
+instance = comp, \inst|knightlight~1275_I\, inst|knightlight~1275, demo_top, 1
+instance = comp, \inst|knightlight~1276_I\, inst|knightlight~1276, demo_top, 1
+instance = comp, \inst|knightlight[1]~I\, inst|knightlight[1], demo_top, 1
+instance = comp, \inst|ledstate_next~431_I\, inst|ledstate_next~431, demo_top, 1
+instance = comp, \inst|ledstate_next~432_I\, inst|ledstate_next~432, demo_top, 1
+instance = comp, \inst|ledstate_next~433_I\, inst|ledstate_next~433, demo_top, 1
+instance = comp, \inst|ledstate_next~436_I\, inst|ledstate_next~436, demo_top, 1
+instance = comp, \inst|ledstate~I\, inst|ledstate, demo_top, 1
+instance = comp, \inst|knightlight~1267_I\, inst|knightlight~1267, demo_top, 1
+instance = comp, \inst|knightlight~1268_I\, inst|knightlight~1268, demo_top, 1
+instance = comp, \inst|knightlight[5]~I\, inst|knightlight[5], demo_top, 1
+instance = comp, \inst|knightlight~1265_I\, inst|knightlight~1265, demo_top, 1
+instance = comp, \inst|knightlight~1266_I\, inst|knightlight~1266, demo_top, 1
+instance = comp, \inst|knightlight[6]~I\, inst|knightlight[6], demo_top, 1
+instance = comp, \inst|knightlight~1264_I\, inst|knightlight~1264, demo_top, 1
+instance = comp, \inst|knightlight[7]~I\, inst|knightlight[7], demo_top, 1
+instance = comp, \LEDS[7]~I\, LEDS[7], demo_top, 1
+instance = comp, \LEDS[6]~I\, LEDS[6], demo_top, 1
+instance = comp, \LEDS[5]~I\, LEDS[5], demo_top, 1
+instance = comp, \LEDS[4]~I\, LEDS[4], demo_top, 1
+instance = comp, \LEDS[3]~I\, LEDS[3], demo_top, 1
+instance = comp, \LEDS[2]~I\, LEDS[2], demo_top, 1
+instance = comp, \LEDS[1]~I\, LEDS[1], demo_top, 1
+instance = comp, \LEDS[0]~I\, LEDS[0], demo_top, 1
hardware-modellierung VL (ss10)