--- /dev/null
+Classic Timing Analyzer report for demo
+Mon Mar 30 19:53:32 2009
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Timing Analyzer Summary
+ 3. Timing Analyzer Settings
+ 4. Clock Settings Summary
+ 5. Clock Setup: 'pll:inst1|altpll:altpll_component|_clk0'
+ 6. Clock Hold: 'pll:inst1|altpll:altpll_component|_clk0'
+ 7. tsu
+ 8. tco
+ 9. th
+ 10. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++--------------------------------------------------------+----------+-----------------------------------+----------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++--------------------------------------------------------+----------+-----------------------------------+----------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+--------------+
+; Worst-case tsu ; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[5] ; -- ; CLK ; 0 ;
+; Worst-case tco ; N/A ; None ; 9.507 ns ; demo:inst|knightlight[0] ; LEDS[0] ; CLK ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; -7.313 ns ; RESET ; demo:inst|counter[2] ; -- ; CLK ; 0 ;
+; Clock Setup: 'pll:inst1|altpll:altpll_component|_clk0' ; 3.604 ns ; 100.00 MHz ( period = 10.000 ns ) ; 156.35 MHz ( period = 6.396 ns ) ; demo:inst|counter[3] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0 ;
+; Clock Hold: 'pll:inst1|altpll:altpll_component|_clk0' ; 0.391 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A ; demo:inst|knightlight[5] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++--------------------------------------------------------+----------+-----------------------------------+----------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Settings ;
++-------------------------------------------------------+--------------------+------+----+-------------+
+; Option ; Setting ; From ; To ; Entity Name ;
++-------------------------------------------------------+--------------------+------+----+-------------+
+; Device Name ; EP2C35F484C6 ; ; ; ;
+; Timing Models ; Final ; ; ; ;
+; Default hold multicycle ; Same as Multicycle ; ; ; ;
+; Cut paths between unrelated clock domains ; On ; ; ; ;
+; Cut off read during write signal paths ; On ; ; ; ;
+; Cut off feedback from I/O pins ; On ; ; ; ;
+; Report Combined Fast/Slow Timing ; Off ; ; ; ;
+; Ignore Clock Settings ; Off ; ; ; ;
+; Analyze latches as synchronous elements ; On ; ; ; ;
+; Enable Recovery/Removal analysis ; Off ; ; ; ;
+; Enable Clock Latency ; Off ; ; ; ;
+; Number of source nodes to report per destination node ; 10 ; ; ; ;
+; Number of destination nodes to report ; 10 ; ; ; ;
+; Number of paths to report ; 200 ; ; ; ;
+; Report Minimum Timing Checks ; Off ; ; ; ;
+; Use Fast Timing Models ; Off ; ; ; ;
+; Report IO Paths Separately ; Off ; ; ; ;
++-------------------------------------------------------+--------------------+------+----+-------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Settings Summary ;
++-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
++-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+; pll:inst1|altpll:altpll_component|_clk0 ; ; PLL output ; 100.0 MHz ; 0.000 ns ; 0.000 ns ; CLK ; 4 ; 1 ; -2.378 ns ; ;
+; CLK ; ; User Pin ; 25.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
++-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'pll:inst1|altpll:altpll_component|_clk0' ;
++----------+---------------------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++----------+---------------------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
+; 3.604 ns ; 156.35 MHz ( period = 6.396 ns ) ; demo:inst|counter[3] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.182 ns ;
+; 3.606 ns ; 156.40 MHz ( period = 6.394 ns ) ; demo:inst|counter[3] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.180 ns ;
+; 3.607 ns ; 156.42 MHz ( period = 6.393 ns ) ; demo:inst|counter[3] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.179 ns ;
+; 3.608 ns ; 156.45 MHz ( period = 6.392 ns ) ; demo:inst|counter[0] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.178 ns ;
+; 3.610 ns ; 156.49 MHz ( period = 6.390 ns ) ; demo:inst|counter[0] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.176 ns ;
+; 3.611 ns ; 156.52 MHz ( period = 6.389 ns ) ; demo:inst|counter[0] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.175 ns ;
+; 3.725 ns ; 159.36 MHz ( period = 6.275 ns ) ; demo:inst|counter[4] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.061 ns ;
+; 3.727 ns ; 159.41 MHz ( period = 6.273 ns ) ; demo:inst|counter[4] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.059 ns ;
+; 3.728 ns ; 159.44 MHz ( period = 6.272 ns ) ; demo:inst|counter[4] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.058 ns ;
+; 3.753 ns ; 160.08 MHz ( period = 6.247 ns ) ; demo:inst|counter[5] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.033 ns ;
+; 3.755 ns ; 160.13 MHz ( period = 6.245 ns ) ; demo:inst|counter[5] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.031 ns ;
+; 3.756 ns ; 160.15 MHz ( period = 6.244 ns ) ; demo:inst|counter[5] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.030 ns ;
+; 3.809 ns ; 161.52 MHz ( period = 6.191 ns ) ; demo:inst|counter[1] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.977 ns ;
+; 3.811 ns ; 161.58 MHz ( period = 6.189 ns ) ; demo:inst|counter[1] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.975 ns ;
+; 3.812 ns ; 161.60 MHz ( period = 6.188 ns ) ; demo:inst|counter[1] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.974 ns ;
+; 3.863 ns ; 162.95 MHz ( period = 6.137 ns ) ; demo:inst|counter[6] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.923 ns ;
+; 3.865 ns ; 163.00 MHz ( period = 6.135 ns ) ; demo:inst|counter[6] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.921 ns ;
+; 3.866 ns ; 163.03 MHz ( period = 6.134 ns ) ; demo:inst|counter[6] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.920 ns ;
+; 3.903 ns ; 164.02 MHz ( period = 6.097 ns ) ; demo:inst|counter[3] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.883 ns ;
+; 3.907 ns ; 164.12 MHz ( period = 6.093 ns ) ; demo:inst|counter[0] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.879 ns ;
+; 3.979 ns ; 166.09 MHz ( period = 6.021 ns ) ; demo:inst|counter[2] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.807 ns ;
+; 3.981 ns ; 166.14 MHz ( period = 6.019 ns ) ; demo:inst|counter[2] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.805 ns ;
+; 3.982 ns ; 166.17 MHz ( period = 6.018 ns ) ; demo:inst|counter[2] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.804 ns ;
+; 4.012 ns ; 167.00 MHz ( period = 5.988 ns ) ; demo:inst|counter[3] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.774 ns ;
+; 4.013 ns ; 167.03 MHz ( period = 5.987 ns ) ; demo:inst|counter[3] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.773 ns ;
+; 4.015 ns ; 167.08 MHz ( period = 5.985 ns ) ; demo:inst|counter[3] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.771 ns ;
+; 4.016 ns ; 167.11 MHz ( period = 5.984 ns ) ; demo:inst|counter[0] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.770 ns ;
+; 4.017 ns ; 167.14 MHz ( period = 5.983 ns ) ; demo:inst|counter[0] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.769 ns ;
+; 4.019 ns ; 167.20 MHz ( period = 5.981 ns ) ; demo:inst|counter[0] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.767 ns ;
+; 4.024 ns ; 167.34 MHz ( period = 5.976 ns ) ; demo:inst|counter[4] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.762 ns ;
+; 4.052 ns ; 168.12 MHz ( period = 5.948 ns ) ; demo:inst|counter[5] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.734 ns ;
+; 4.108 ns ; 169.72 MHz ( period = 5.892 ns ) ; demo:inst|counter[1] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.678 ns ;
+; 4.133 ns ; 170.44 MHz ( period = 5.867 ns ) ; demo:inst|counter[4] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.653 ns ;
+; 4.134 ns ; 170.47 MHz ( period = 5.866 ns ) ; demo:inst|counter[4] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.652 ns ;
+; 4.136 ns ; 170.53 MHz ( period = 5.864 ns ) ; demo:inst|counter[4] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.650 ns ;
+; 4.161 ns ; 171.26 MHz ( period = 5.839 ns ) ; demo:inst|counter[5] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.625 ns ;
+; 4.162 ns ; 171.29 MHz ( period = 5.838 ns ) ; demo:inst|counter[5] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.624 ns ;
+; 4.162 ns ; 171.29 MHz ( period = 5.838 ns ) ; demo:inst|counter[6] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.624 ns ;
+; 4.164 ns ; 171.35 MHz ( period = 5.836 ns ) ; demo:inst|counter[5] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.622 ns ;
+; 4.217 ns ; 172.92 MHz ( period = 5.783 ns ) ; demo:inst|counter[1] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.569 ns ;
+; 4.218 ns ; 172.95 MHz ( period = 5.782 ns ) ; demo:inst|counter[1] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.568 ns ;
+; 4.220 ns ; 173.01 MHz ( period = 5.780 ns ) ; demo:inst|counter[1] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.566 ns ;
+; 4.271 ns ; 174.55 MHz ( period = 5.729 ns ) ; demo:inst|counter[6] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.515 ns ;
+; 4.272 ns ; 174.58 MHz ( period = 5.728 ns ) ; demo:inst|counter[6] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.514 ns ;
+; 4.274 ns ; 174.64 MHz ( period = 5.726 ns ) ; demo:inst|counter[6] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.512 ns ;
+; 4.278 ns ; 174.76 MHz ( period = 5.722 ns ) ; demo:inst|counter[2] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.508 ns ;
+; 4.387 ns ; 178.16 MHz ( period = 5.613 ns ) ; demo:inst|counter[2] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.399 ns ;
+; 4.388 ns ; 178.19 MHz ( period = 5.612 ns ) ; demo:inst|counter[2] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.398 ns ;
+; 4.390 ns ; 178.25 MHz ( period = 5.610 ns ) ; demo:inst|counter[2] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.396 ns ;
+; 4.740 ns ; 190.11 MHz ( period = 5.260 ns ) ; demo:inst|counter[4] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.998 ns ;
+; 4.959 ns ; 198.37 MHz ( period = 5.041 ns ) ; demo:inst|counter[3] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.779 ns ;
+; 5.075 ns ; 203.05 MHz ( period = 4.925 ns ) ; demo:inst|counter[6] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.663 ns ;
+; 5.098 ns ; 204.00 MHz ( period = 4.902 ns ) ; demo:inst|knightlight[3] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 4.688 ns ;
+; 5.177 ns ; 207.34 MHz ( period = 4.823 ns ) ; demo:inst|counter[0] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.561 ns ;
+; 5.337 ns ; 214.45 MHz ( period = 4.663 ns ) ; demo:inst|counter[1] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.401 ns ;
+; 5.484 ns ; 221.43 MHz ( period = 4.516 ns ) ; demo:inst|counter[2] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.254 ns ;
+; 5.491 ns ; 221.78 MHz ( period = 4.509 ns ) ; demo:inst|counter[5] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.247 ns ;
+; 5.761 ns ; 235.90 MHz ( period = 4.239 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.977 ns ;
+; 5.763 ns ; 236.02 MHz ( period = 4.237 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.975 ns ;
+; 5.764 ns ; 236.07 MHz ( period = 4.236 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.974 ns ;
+; 5.980 ns ; 248.76 MHz ( period = 4.020 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.758 ns ;
+; 5.982 ns ; 248.88 MHz ( period = 4.018 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.756 ns ;
+; 5.983 ns ; 248.94 MHz ( period = 4.017 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.755 ns ;
+; 6.008 ns ; 250.50 MHz ( period = 3.992 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.730 ns ;
+; 6.009 ns ; 250.56 MHz ( period = 3.991 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.729 ns ;
+; 6.039 ns ; 252.46 MHz ( period = 3.961 ns ) ; demo:inst|knightlight[2] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.740 ns ; 3.701 ns ;
+; 6.096 ns ; 256.15 MHz ( period = 3.904 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.642 ns ;
+; 6.098 ns ; 256.28 MHz ( period = 3.902 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.640 ns ;
+; 6.099 ns ; 256.34 MHz ( period = 3.901 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.639 ns ;
+; 6.198 ns ; 263.02 MHz ( period = 3.802 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.540 ns ;
+; 6.200 ns ; 263.16 MHz ( period = 3.800 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.538 ns ;
+; 6.201 ns ; 263.23 MHz ( period = 3.799 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.537 ns ;
+; 6.227 ns ; 265.04 MHz ( period = 3.773 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.511 ns ;
+; 6.228 ns ; 265.11 MHz ( period = 3.772 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.510 ns ;
+; 6.343 ns ; 273.45 MHz ( period = 3.657 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.395 ns ;
+; 6.344 ns ; 273.52 MHz ( period = 3.656 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.394 ns ;
+; 6.358 ns ; 274.57 MHz ( period = 3.642 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.380 ns ;
+; 6.360 ns ; 274.73 MHz ( period = 3.640 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.378 ns ;
+; 6.361 ns ; 274.80 MHz ( period = 3.639 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.377 ns ;
+; 6.445 ns ; 281.29 MHz ( period = 3.555 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.293 ns ;
+; 6.446 ns ; 281.37 MHz ( period = 3.554 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.292 ns ;
+; 6.505 ns ; 286.12 MHz ( period = 3.495 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.233 ns ;
+; 6.507 ns ; 286.29 MHz ( period = 3.493 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.231 ns ;
+; 6.508 ns ; 286.37 MHz ( period = 3.492 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.230 ns ;
+; 6.512 ns ; 286.70 MHz ( period = 3.488 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.226 ns ;
+; 6.514 ns ; 286.86 MHz ( period = 3.486 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.224 ns ;
+; 6.515 ns ; 286.94 MHz ( period = 3.485 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.223 ns ;
+; 6.531 ns ; 288.27 MHz ( period = 3.469 ns ) ; demo:inst|knightlight[3] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.832 ns ; 3.301 ns ;
+; 6.605 ns ; 294.55 MHz ( period = 3.395 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.133 ns ;
+; 6.606 ns ; 294.64 MHz ( period = 3.394 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.132 ns ;
+; 6.686 ns ; 301.75 MHz ( period = 3.314 ns ) ; demo:inst|knightlight[2] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.740 ns ; 3.054 ns ;
+; 6.717 ns ; 304.60 MHz ( period = 3.283 ns ) ; demo:inst|knightlight[1] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.740 ns ; 3.023 ns ;
+; 6.752 ns ; 307.88 MHz ( period = 3.248 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 2.986 ns ;
+; 6.753 ns ; 307.98 MHz ( period = 3.247 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 2.985 ns ;
+; 6.759 ns ; 308.55 MHz ( period = 3.241 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 2.979 ns ;
+; 6.760 ns ; 308.64 MHz ( period = 3.240 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 2.978 ns ;
+; 6.849 ns ; 317.36 MHz ( period = 3.151 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.832 ns ; 2.983 ns ;
+; 6.862 ns ; 318.67 MHz ( period = 3.138 ns ) ; demo:inst|knightlight[0] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.740 ns ; 2.878 ns ;
+; 6.863 ns ; 318.78 MHz ( period = 3.137 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.832 ns ; 2.969 ns ;
+; 7.127 ns ; 348.07 MHz ( period = 2.873 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.832 ns ; 2.705 ns ;
+; 7.239 ns ; 362.19 MHz ( period = 2.761 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.545 ns ;
+; 7.242 ns ; 362.58 MHz ( period = 2.758 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.542 ns ;
+; 7.246 ns ; 363.11 MHz ( period = 2.754 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.538 ns ;
+; 7.458 ns ; 393.39 MHz ( period = 2.542 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.326 ns ;
+; 7.461 ns ; 393.86 MHz ( period = 2.539 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.323 ns ;
+; 7.465 ns ; 394.48 MHz ( period = 2.535 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.319 ns ;
+; 7.574 ns ; 412.20 MHz ( period = 2.426 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.210 ns ;
+; 7.577 ns ; 412.71 MHz ( period = 2.423 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.207 ns ;
+; 7.581 ns ; 413.39 MHz ( period = 2.419 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.203 ns ;
+; 7.676 ns ; 430.29 MHz ( period = 2.324 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.108 ns ;
+; 7.679 ns ; 430.85 MHz ( period = 2.321 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.105 ns ;
+; 7.683 ns ; 431.59 MHz ( period = 2.317 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.101 ns ;
+; 7.836 ns ; 462.11 MHz ( period = 2.164 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.948 ns ;
+; 7.839 ns ; 462.75 MHz ( period = 2.161 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.945 ns ;
+; 7.843 ns ; 463.61 MHz ( period = 2.157 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.941 ns ;
+; 7.983 ns ; 495.79 MHz ( period = 2.017 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.801 ns ;
+; 7.986 ns ; 496.52 MHz ( period = 2.014 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.798 ns ;
+; 7.990 ns ; 497.51 MHz ( period = 2.010 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.794 ns ;
+; 7.990 ns ; 497.51 MHz ( period = 2.010 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.794 ns ;
+; 7.993 ns ; 498.26 MHz ( period = 2.007 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.791 ns ;
+; 7.997 ns ; 499.25 MHz ( period = 2.003 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.787 ns ;
+; 8.036 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[6] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.750 ns ;
+; 8.158 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[5] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.628 ns ;
+; 8.171 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.615 ns ;
+; 8.227 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.559 ns ;
+; 8.233 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[4] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.553 ns ;
+; 8.360 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[7] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.426 ns ;
+; 8.391 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[3] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.395 ns ;
+; 8.536 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[1] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.250 ns ;
+; 8.539 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[5] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.247 ns ;
+; 8.544 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[5] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.242 ns ;
+; 8.556 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[6] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.230 ns ;
+; 8.572 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[2] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.214 ns ;
+; 8.651 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.135 ns ;
+; 8.654 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.132 ns ;
+; 8.661 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.125 ns ;
+; 8.670 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[7] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.116 ns ;
+; 8.804 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[4] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.982 ns ;
+; 8.818 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[4] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.968 ns ;
+; 8.832 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[0] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.954 ns ;
+; 8.878 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.908 ns ;
+; 8.953 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[6] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.833 ns ;
+; 9.038 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[1] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.748 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[5] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[3] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[0] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[1] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[2] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[4] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[6] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[7] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
++----------+---------------------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'pll:inst1|altpll:altpll_component|_clk0' ;
++---------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++---------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+----------------------------+----------------------------+--------------------------+
+; 0.391 ns ; demo:inst|knightlight[5] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[3] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[0] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[1] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[2] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[4] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|counter[0] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[6] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|ledstate ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[7] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.732 ns ; demo:inst|knightlight[1] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.748 ns ;
+; 0.817 ns ; demo:inst|knightlight[6] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.833 ns ;
+; 0.892 ns ; demo:inst|ledstate ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.908 ns ;
+; 0.938 ns ; demo:inst|knightlight[0] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.954 ns ;
+; 0.952 ns ; demo:inst|knightlight[4] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.968 ns ;
+; 0.966 ns ; demo:inst|knightlight[4] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.982 ns ;
+; 1.100 ns ; demo:inst|knightlight[7] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.116 ns ;
+; 1.109 ns ; demo:inst|ledstate ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.125 ns ;
+; 1.116 ns ; demo:inst|ledstate ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.132 ns ;
+; 1.119 ns ; demo:inst|ledstate ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.135 ns ;
+; 1.198 ns ; demo:inst|knightlight[2] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.214 ns ;
+; 1.214 ns ; demo:inst|knightlight[6] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.230 ns ;
+; 1.226 ns ; demo:inst|knightlight[5] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.242 ns ;
+; 1.231 ns ; demo:inst|knightlight[5] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.247 ns ;
+; 1.234 ns ; demo:inst|knightlight[1] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.250 ns ;
+; 1.337 ns ; demo:inst|counter[1] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.353 ns ;
+; 1.379 ns ; demo:inst|knightlight[3] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.395 ns ;
+; 1.410 ns ; demo:inst|knightlight[7] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.426 ns ;
+; 1.518 ns ; demo:inst|counter[2] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.534 ns ;
+; 1.536 ns ; demo:inst|counter[0] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.552 ns ;
+; 1.537 ns ; demo:inst|knightlight[4] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.553 ns ;
+; 1.543 ns ; demo:inst|ledstate ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.559 ns ;
+; 1.612 ns ; demo:inst|knightlight[5] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.628 ns ;
+; 1.734 ns ; demo:inst|knightlight[6] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.750 ns ;
+; 1.773 ns ; demo:inst|counter[5] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.787 ns ;
+; 1.777 ns ; demo:inst|counter[5] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.791 ns ;
+; 1.780 ns ; demo:inst|counter[2] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.794 ns ;
+; 1.780 ns ; demo:inst|counter[5] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.794 ns ;
+; 1.784 ns ; demo:inst|counter[2] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.798 ns ;
+; 1.787 ns ; demo:inst|counter[2] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.801 ns ;
+; 1.927 ns ; demo:inst|counter[1] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.941 ns ;
+; 1.931 ns ; demo:inst|counter[1] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.945 ns ;
+; 1.934 ns ; demo:inst|counter[1] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.948 ns ;
+; 1.967 ns ; demo:inst|knightlight[3] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.983 ns ;
+; 2.000 ns ; demo:inst|counter[1] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 2.016 ns ;
+; 2.087 ns ; demo:inst|counter[0] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.101 ns ;
+; 2.091 ns ; demo:inst|counter[0] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.105 ns ;
+; 2.094 ns ; demo:inst|counter[0] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.108 ns ;
+; 2.189 ns ; demo:inst|counter[6] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.203 ns ;
+; 2.193 ns ; demo:inst|counter[6] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.207 ns ;
+; 2.196 ns ; demo:inst|counter[6] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.210 ns ;
+; 2.201 ns ; demo:inst|counter[0] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 2.217 ns ;
+; 2.305 ns ; demo:inst|counter[3] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.319 ns ;
+; 2.309 ns ; demo:inst|counter[3] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.323 ns ;
+; 2.312 ns ; demo:inst|counter[3] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.326 ns ;
+; 2.524 ns ; demo:inst|counter[4] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.538 ns ;
+; 2.528 ns ; demo:inst|counter[4] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.542 ns ;
+; 2.531 ns ; demo:inst|counter[4] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.545 ns ;
+; 2.643 ns ; demo:inst|ledstate ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.062 ns ; 2.705 ns ;
+; 2.790 ns ; demo:inst|counter[6] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 2.806 ns ;
+; 2.907 ns ; demo:inst|ledstate ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.062 ns ; 2.969 ns ;
+; 2.908 ns ; demo:inst|knightlight[0] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.030 ns ; 2.878 ns ;
+; 2.921 ns ; demo:inst|ledstate ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.062 ns ; 2.983 ns ;
+; 2.931 ns ; demo:inst|counter[5] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 2.947 ns ;
+; 2.948 ns ; demo:inst|counter[2] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 2.964 ns ;
+; 2.986 ns ; demo:inst|counter[2] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.002 ns ;
+; 3.010 ns ; demo:inst|counter[5] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 2.978 ns ;
+; 3.011 ns ; demo:inst|counter[5] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 2.979 ns ;
+; 3.017 ns ; demo:inst|counter[2] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 2.985 ns ;
+; 3.018 ns ; demo:inst|counter[2] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 2.986 ns ;
+; 3.019 ns ; demo:inst|counter[2] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.035 ns ;
+; 3.046 ns ; demo:inst|counter[3] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.062 ns ;
+; 3.053 ns ; demo:inst|knightlight[1] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.030 ns ; 3.023 ns ;
+; 3.084 ns ; demo:inst|knightlight[2] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.030 ns ; 3.054 ns ;
+; 3.093 ns ; demo:inst|counter[4] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.109 ns ;
+; 3.118 ns ; demo:inst|counter[1] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.134 ns ;
+; 3.150 ns ; demo:inst|counter[2] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.166 ns ;
+; 3.156 ns ; demo:inst|counter[1] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.172 ns ;
+; 3.164 ns ; demo:inst|counter[1] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.132 ns ;
+; 3.165 ns ; demo:inst|counter[1] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.133 ns ;
+; 3.175 ns ; demo:inst|counter[5] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.191 ns ;
+; 3.189 ns ; demo:inst|counter[1] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.205 ns ;
+; 3.203 ns ; demo:inst|counter[4] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.219 ns ;
+; 3.239 ns ; demo:inst|knightlight[3] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.062 ns ; 3.301 ns ;
+; 3.255 ns ; demo:inst|counter[5] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.223 ns ;
+; 3.256 ns ; demo:inst|counter[5] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.224 ns ;
+; 3.258 ns ; demo:inst|counter[5] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.226 ns ;
+; 3.262 ns ; demo:inst|counter[2] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.230 ns ;
+; 3.263 ns ; demo:inst|counter[2] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.231 ns ;
+; 3.265 ns ; demo:inst|counter[2] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.233 ns ;
+; 3.274 ns ; demo:inst|counter[4] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.290 ns ;
+; 3.319 ns ; demo:inst|counter[0] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.335 ns ;
+; 3.320 ns ; demo:inst|counter[1] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.336 ns ;
+; 3.323 ns ; demo:inst|counter[3] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.339 ns ;
+; 3.324 ns ; demo:inst|counter[0] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.292 ns ;
+; 3.325 ns ; demo:inst|counter[0] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.293 ns ;
+; 3.337 ns ; demo:inst|knightlight[2] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.030 ns ; 3.307 ns ;
+; 3.357 ns ; demo:inst|counter[0] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.373 ns ;
+; 3.390 ns ; demo:inst|counter[0] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.406 ns ;
+; 3.394 ns ; demo:inst|counter[3] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.410 ns ;
+; 3.409 ns ; demo:inst|counter[1] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.377 ns ;
+; 3.410 ns ; demo:inst|counter[1] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.378 ns ;
+; 3.412 ns ; demo:inst|counter[1] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.380 ns ;
+; 3.426 ns ; demo:inst|counter[6] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.394 ns ;
+; 3.427 ns ; demo:inst|counter[6] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.395 ns ;
+; 3.521 ns ; demo:inst|counter[0] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.537 ns ;
+; 3.525 ns ; demo:inst|counter[3] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.541 ns ;
+; 3.542 ns ; demo:inst|counter[3] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.510 ns ;
+; 3.543 ns ; demo:inst|counter[3] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.511 ns ;
+; 3.569 ns ; demo:inst|counter[0] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.537 ns ;
+; 3.570 ns ; demo:inst|counter[0] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.538 ns ;
+; 3.572 ns ; demo:inst|counter[0] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.540 ns ;
+; 3.671 ns ; demo:inst|counter[6] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.639 ns ;
+; 3.672 ns ; demo:inst|counter[6] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.640 ns ;
+; 3.674 ns ; demo:inst|counter[6] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.642 ns ;
+; 3.761 ns ; demo:inst|counter[4] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.729 ns ;
+; 3.762 ns ; demo:inst|counter[4] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.730 ns ;
+; 3.787 ns ; demo:inst|counter[3] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.755 ns ;
+; 3.788 ns ; demo:inst|counter[3] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.756 ns ;
+; 3.790 ns ; demo:inst|counter[3] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.758 ns ;
+; 3.815 ns ; demo:inst|counter[6] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.831 ns ;
+; 3.817 ns ; demo:inst|counter[6] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.833 ns ;
+; 3.818 ns ; demo:inst|counter[6] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.834 ns ;
+; 3.823 ns ; demo:inst|counter[4] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.839 ns ;
+; 3.875 ns ; demo:inst|counter[5] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.891 ns ;
+; 3.878 ns ; demo:inst|counter[5] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.894 ns ;
+; 4.006 ns ; demo:inst|counter[4] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.974 ns ;
+; 4.007 ns ; demo:inst|counter[4] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.975 ns ;
+; 4.009 ns ; demo:inst|counter[4] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.977 ns ;
+; 4.217 ns ; demo:inst|counter[2] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.233 ns ;
+; 4.220 ns ; demo:inst|counter[2] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.236 ns ;
+; 4.223 ns ; demo:inst|counter[6] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.239 ns ;
+; 4.224 ns ; demo:inst|counter[6] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.240 ns ;
+; 4.226 ns ; demo:inst|counter[6] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.242 ns ;
+; 4.231 ns ; demo:inst|counter[4] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.247 ns ;
+; 4.232 ns ; demo:inst|counter[4] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.248 ns ;
+; 4.234 ns ; demo:inst|counter[4] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.250 ns ;
+; 4.279 ns ; demo:inst|counter[5] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.247 ns ;
+; 4.283 ns ; demo:inst|counter[5] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.299 ns ;
+; 4.284 ns ; demo:inst|counter[5] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.300 ns ;
+; 4.286 ns ; demo:inst|counter[5] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.302 ns ;
+; 4.286 ns ; demo:inst|counter[2] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.254 ns ;
+; 4.390 ns ; demo:inst|counter[3] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.406 ns ;
+; 4.391 ns ; demo:inst|counter[3] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.407 ns ;
+; 4.393 ns ; demo:inst|counter[3] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.409 ns ;
+; 4.433 ns ; demo:inst|counter[1] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.401 ns ;
+; 4.458 ns ; demo:inst|counter[1] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.474 ns ;
+; 4.593 ns ; demo:inst|counter[0] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.561 ns ;
+; 4.695 ns ; demo:inst|counter[6] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.663 ns ;
+; 4.811 ns ; demo:inst|counter[3] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.779 ns ;
+; 5.030 ns ; demo:inst|counter[4] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.998 ns ;
++---------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++---------------------------------------------------------------------------------+
+; tsu ;
++-------+--------------+------------+-------+--------------------------+----------+
+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
++-------+--------------+------------+-------+--------------------------+----------+
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[7] ; CLK ;
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|ledstate ; CLK ;
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[6] ; CLK ;
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[4] ; CLK ;
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[3] ; CLK ;
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[5] ; CLK ;
+; N/A ; None ; 7.693 ns ; RESET ; demo:inst|knightlight[2] ; CLK ;
+; N/A ; None ; 7.693 ns ; RESET ; demo:inst|knightlight[1] ; CLK ;
+; N/A ; None ; 7.693 ns ; RESET ; demo:inst|knightlight[0] ; CLK ;
+; N/A ; None ; 7.545 ns ; RESET ; demo:inst|counter[6] ; CLK ;
+; N/A ; None ; 7.545 ns ; RESET ; demo:inst|counter[4] ; CLK ;
+; N/A ; None ; 7.545 ns ; RESET ; demo:inst|counter[5] ; CLK ;
+; N/A ; None ; 7.545 ns ; RESET ; demo:inst|counter[3] ; CLK ;
+; N/A ; None ; 7.543 ns ; RESET ; demo:inst|counter[0] ; CLK ;
+; N/A ; None ; 7.543 ns ; RESET ; demo:inst|counter[1] ; CLK ;
+; N/A ; None ; 7.543 ns ; RESET ; demo:inst|counter[2] ; CLK ;
++-------+--------------+------------+-------+--------------------------+----------+
+
+
++-------------------------------------------------------------------------------------+
+; tco ;
++-------+--------------+------------+--------------------------+---------+------------+
+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
++-------+--------------+------------+--------------------------+---------+------------+
+; N/A ; None ; 9.507 ns ; demo:inst|knightlight[0] ; LEDS[0] ; CLK ;
+; N/A ; None ; 9.388 ns ; demo:inst|knightlight[2] ; LEDS[2] ; CLK ;
+; N/A ; None ; 9.171 ns ; demo:inst|knightlight[1] ; LEDS[1] ; CLK ;
+; N/A ; None ; 7.540 ns ; demo:inst|knightlight[4] ; LEDS[4] ; CLK ;
+; N/A ; None ; 7.369 ns ; demo:inst|knightlight[7] ; LEDS[7] ; CLK ;
+; N/A ; None ; 6.654 ns ; demo:inst|knightlight[3] ; LEDS[3] ; CLK ;
+; N/A ; None ; 6.178 ns ; demo:inst|knightlight[5] ; LEDS[5] ; CLK ;
+; N/A ; None ; 6.126 ns ; demo:inst|knightlight[6] ; LEDS[6] ; CLK ;
++-------+--------------+------------+--------------------------+---------+------------+
+
+
++---------------------------------------------------------------------------------------+
+; th ;
++---------------+-------------+-----------+-------+--------------------------+----------+
+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
++---------------+-------------+-----------+-------+--------------------------+----------+
+; N/A ; None ; -7.313 ns ; RESET ; demo:inst|counter[0] ; CLK ;
+; N/A ; None ; -7.313 ns ; RESET ; demo:inst|counter[1] ; CLK ;
+; N/A ; None ; -7.313 ns ; RESET ; demo:inst|counter[2] ; CLK ;
+; N/A ; None ; -7.315 ns ; RESET ; demo:inst|counter[6] ; CLK ;
+; N/A ; None ; -7.315 ns ; RESET ; demo:inst|counter[4] ; CLK ;
+; N/A ; None ; -7.315 ns ; RESET ; demo:inst|counter[5] ; CLK ;
+; N/A ; None ; -7.315 ns ; RESET ; demo:inst|counter[3] ; CLK ;
+; N/A ; None ; -7.463 ns ; RESET ; demo:inst|knightlight[2] ; CLK ;
+; N/A ; None ; -7.463 ns ; RESET ; demo:inst|knightlight[1] ; CLK ;
+; N/A ; None ; -7.463 ns ; RESET ; demo:inst|knightlight[0] ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|knightlight[7] ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|ledstate ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|knightlight[6] ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|knightlight[4] ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|knightlight[3] ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|knightlight[5] ; CLK ;
++---------------+-------------+-----------+-------+--------------------------+----------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Classic Timing Analyzer
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:53:31 2009
+Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off demo -c demo --timing_analysis_only
+Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
+Info: Found timing assignments -- calculating delays
+Info: Slack time is 3.604 ns for clock "pll:inst1|altpll:altpll_component|_clk0" between source register "demo:inst|counter[3]" and destination register "demo:inst|counter[1]"
+ Info: Fmax is 156.35 MHz (period= 6.396 ns)
+ Info: + Largest register to register requirement is 9.786 ns
+ Info: + Setup relationship between source and destination is 10.000 ns
+ Info: + Latch edge is 7.622 ns
+ Info: Clock period of Destination clock "pll:inst1|altpll:altpll_component|_clk0" is 10.000 ns with offset of -2.378 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Destination register is 1
+ Info: - Launch edge is -2.378 ns
+ Info: Clock period of Source clock "pll:inst1|altpll:altpll_component|_clk0" is 10.000 ns with offset of -2.378 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Source register is 1
+ Info: + Largest clock skew is 0.000 ns
+ Info: + Shortest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to destination register is 2.650 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X55_Y31_N1; Fanout = 3; REG Node = 'demo:inst|counter[1]'
+ Info: Total cell delay = 0.537 ns ( 20.26 % )
+ Info: Total interconnect delay = 2.113 ns ( 79.74 % )
+ Info: - Longest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to source register is 2.650 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X57_Y31_N31; Fanout = 3; REG Node = 'demo:inst|counter[3]'
+ Info: Total cell delay = 0.537 ns ( 20.26 % )
+ Info: Total interconnect delay = 2.113 ns ( 79.74 % )
+ Info: - Micro clock to output delay of source is 0.250 ns
+ Info: - Micro setup delay of destination is -0.036 ns
+ Info: - Longest register to register delay is 6.182 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X57_Y31_N31; Fanout = 3; REG Node = 'demo:inst|counter[3]'
+ Info: 2: + IC(0.741 ns) + CELL(0.414 ns) = 1.155 ns; Loc. = LCCOMB_X55_Y31_N18; Fanout = 2; COMB Node = 'demo:inst|Add0~101'
+ Info: 3: + IC(0.000 ns) + CELL(0.410 ns) = 1.565 ns; Loc. = LCCOMB_X55_Y31_N20; Fanout = 3; COMB Node = 'demo:inst|Add0~102'
+ Info: 4: + IC(0.277 ns) + CELL(0.414 ns) = 2.256 ns; Loc. = LCCOMB_X55_Y31_N4; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19'
+ Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.327 ns; Loc. = LCCOMB_X55_Y31_N6; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21'
+ Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.398 ns; Loc. = LCCOMB_X55_Y31_N8; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23'
+ Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.469 ns; Loc. = LCCOMB_X55_Y31_N10; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25'
+ Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 2.879 ns; Loc. = LCCOMB_X55_Y31_N12; Fanout = 14; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26'
+ Info: 9: + IC(0.705 ns) + CELL(0.150 ns) = 3.734 ns; Loc. = LCCOMB_X57_Y31_N10; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22'
+ Info: 10: + IC(0.263 ns) + CELL(0.504 ns) = 4.501 ns; Loc. = LCCOMB_X57_Y31_N14; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21'
+ Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 4.572 ns; Loc. = LCCOMB_X57_Y31_N16; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23'
+ Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 4.643 ns; Loc. = LCCOMB_X57_Y31_N18; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25'
+ Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 4.714 ns; Loc. = LCCOMB_X57_Y31_N20; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27'
+ Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 4.785 ns; Loc. = LCCOMB_X57_Y31_N22; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29'
+ Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 4.856 ns; Loc. = LCCOMB_X57_Y31_N24; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31'
+ Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 5.266 ns; Loc. = LCCOMB_X57_Y31_N26; Fanout = 7; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32'
+ Info: 17: + IC(0.682 ns) + CELL(0.150 ns) = 6.098 ns; Loc. = LCCOMB_X55_Y31_N0; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636'
+ Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 6.182 ns; Loc. = LCFF_X55_Y31_N1; Fanout = 3; REG Node = 'demo:inst|counter[1]'
+ Info: Total cell delay = 3.514 ns ( 56.84 % )
+ Info: Total interconnect delay = 2.668 ns ( 43.16 % )
+Info: No valid register-to-register data paths exist for clock "CLK"
+Info: Minimum slack time is 391 ps for clock "pll:inst1|altpll:altpll_component|_clk0" between source register "demo:inst|knightlight[5]" and destination register "demo:inst|knightlight[5]"
+ Info: + Shortest register to register delay is 0.407 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst|knightlight[5]'
+ Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X33_Y27_N28; Fanout = 1; COMB Node = 'demo:inst|knightlight~1268'
+ Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst|knightlight[5]'
+ Info: Total cell delay = 0.407 ns ( 100.00 % )
+ Info: - Smallest register to register requirement is 0.016 ns
+ Info: + Hold relationship between source and destination is 0.000 ns
+ Info: + Latch edge is -2.378 ns
+ Info: Clock period of Destination clock "pll:inst1|altpll:altpll_component|_clk0" is 10.000 ns with offset of -2.378 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Destination register is 1
+ Info: Multicycle Hold factor for Destination register is 1
+ Info: - Launch edge is -2.378 ns
+ Info: Clock period of Source clock "pll:inst1|altpll:altpll_component|_clk0" is 10.000 ns with offset of -2.378 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Source register is 1
+ Info: Multicycle Hold factor for Source register is 1
+ Info: + Smallest clock skew is 0.000 ns
+ Info: + Longest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to destination register is 2.602 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst|knightlight[5]'
+ Info: Total cell delay = 0.537 ns ( 20.64 % )
+ Info: Total interconnect delay = 2.065 ns ( 79.36 % )
+ Info: - Shortest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to source register is 2.602 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst|knightlight[5]'
+ Info: Total cell delay = 0.537 ns ( 20.64 % )
+ Info: Total interconnect delay = 2.065 ns ( 79.36 % )
+ Info: - Micro clock to output delay of source is 0.250 ns
+ Info: + Micro hold delay of destination is 0.266 ns
+Info: tsu for register "demo:inst|knightlight[7]" (data pin = "RESET", clock pin = "CLK") is 7.774 ns
+ Info: + Longest pin to register delay is 8.034 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B3; Fanout = 16; PIN Node = 'RESET'
+ Info: 2: + IC(6.674 ns) + CELL(0.510 ns) = 8.034 ns; Loc. = LCFF_X33_Y27_N15; Fanout = 4; REG Node = 'demo:inst|knightlight[7]'
+ Info: Total cell delay = 1.360 ns ( 16.93 % )
+ Info: Total interconnect delay = 6.674 ns ( 83.07 % )
+ Info: + Micro setup delay of destination is -0.036 ns
+ Info: - Offset between input clock "CLK" and output clock "pll:inst1|altpll:altpll_component|_clk0" is -2.378 ns
+ Info: - Shortest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to destination register is 2.602 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N15; Fanout = 4; REG Node = 'demo:inst|knightlight[7]'
+ Info: Total cell delay = 0.537 ns ( 20.64 % )
+ Info: Total interconnect delay = 2.065 ns ( 79.36 % )
+Info: tco from clock "CLK" to destination pin "LEDS[0]" through register "demo:inst|knightlight[0]" is 9.507 ns
+ Info: + Offset between input clock "CLK" and output clock "pll:inst1|altpll:altpll_component|_clk0" is -2.378 ns
+ Info: + Longest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to source register is 2.648 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.648 ns; Loc. = LCFF_X54_Y31_N19; Fanout = 4; REG Node = 'demo:inst|knightlight[0]'
+ Info: Total cell delay = 0.537 ns ( 20.28 % )
+ Info: Total interconnect delay = 2.111 ns ( 79.72 % )
+ Info: + Micro clock to output delay of source is 0.250 ns
+ Info: + Longest register to pin delay is 8.987 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X54_Y31_N19; Fanout = 4; REG Node = 'demo:inst|knightlight[0]'
+ Info: 2: + IC(6.365 ns) + CELL(2.622 ns) = 8.987 ns; Loc. = PIN_W5; Fanout = 0; PIN Node = 'LEDS[0]'
+ Info: Total cell delay = 2.622 ns ( 29.18 % )
+ Info: Total interconnect delay = 6.365 ns ( 70.82 % )
+Info: th for register "demo:inst|counter[0]" (data pin = "RESET", clock pin = "CLK") is -7.313 ns
+ Info: + Offset between input clock "CLK" and output clock "pll:inst1|altpll:altpll_component|_clk0" is -2.378 ns
+ Info: + Longest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to destination register is 2.650 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X55_Y31_N29; Fanout = 5; REG Node = 'demo:inst|counter[0]'
+ Info: Total cell delay = 0.537 ns ( 20.26 % )
+ Info: Total interconnect delay = 2.113 ns ( 79.74 % )
+ Info: + Micro hold delay of destination is 0.266 ns
+ Info: - Shortest pin to register delay is 7.851 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B3; Fanout = 16; PIN Node = 'RESET'
+ Info: 2: + IC(6.491 ns) + CELL(0.510 ns) = 7.851 ns; Loc. = LCFF_X55_Y31_N29; Fanout = 5; REG Node = 'demo:inst|counter[0]'
+ Info: Total cell delay = 1.360 ns ( 17.32 % )
+ Info: Total interconnect delay = 6.491 ns ( 82.68 % )
+Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details.
+Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
+ Info: Processing ended: Mon Mar 30 19:53:32 2009
+ Info: Elapsed time: 00:00:01
+
+
projects / hwmod.git / blobdiff