--- /dev/null
+Analysis & Synthesis report for demo
+Mon Mar 30 19:52:38 2009
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Analysis & Synthesis Source Files Read
+ 5. Analysis & Synthesis Resource Usage Summary
+ 6. Analysis & Synthesis Resource Utilization by Entity
+ 7. General Register Statistics
+ 8. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 9. Parameter Settings for User Entity Instance: pll:inst1|altpll:altpll_component
+ 10. Parameter Settings for Inferred Entity Instance: demo:inst|lpm_divide:Mod0
+ 11. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++------------------------------------+-----------------------------------------+
+; Analysis & Synthesis Status ; Successful - Mon Mar 30 19:52:38 2009 ;
+; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
+; Revision Name ; demo ;
+; Top-level Entity Name ; demo_top ;
+; Family ; Cyclone II ;
+; Total logic elements ; 73 ;
+; Total combinational functions ; 73 ;
+; Dedicated logic registers ; 16 ;
+; Total registers ; N/A until Partition Merge ;
+; Total pins ; N/A until Partition Merge ;
+; Total virtual pins ; N/A until Partition Merge ;
+; Total memory bits ; N/A until Partition Merge ;
+; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
+; Total PLLs ; N/A until Partition Merge ;
++------------------------------------+-----------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++--------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP2C35F484C6 ; ;
+; Top-level entity name ; demo_top ; demo ;
+; Family name ; Cyclone II ; Stratix ;
+; Type of Retiming Performed During Resynthesis ; Full ; ;
+; Resynthesis Optimization Effort ; Normal ; ;
+; Physical Synthesis Level for Resynthesis ; Normal ; ;
+; Use Generated Physical Constraints File ; On ; ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL93 ; VHDL93 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique -- Cyclone II ; Balanced ; Balanced ;
+; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Perform gate-level register retiming ; Off ; Off ;
+; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto Shift Register Replacement ; On ; On ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Use smart compilation ; Off ; Off ;
++--------------------------------------------------------------------+--------------------+--------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------------------------+
+; ../src/demo_pkg.vhd ; yes ; User VHDL File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_pkg.vhd ;
+; ../src/demo.vhd ; yes ; User VHDL File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd ;
+; ../src/pll.vhd ; yes ; User VHDL File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd ;
+; ../src/demo_top.bdf ; yes ; User Block Diagram/Schematic File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf ;
+; altpll.tdf ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/altpll.tdf ;
+; aglobal70.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/aglobal70.inc ;
+; stratix_pll.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/stratix_pll.inc ;
+; stratixii_pll.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/stratixii_pll.inc ;
+; cycloneii_pll.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/cycloneii_pll.inc ;
+; lpm_divide.tdf ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/lpm_divide.tdf ;
+; abs_divider.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/abs_divider.inc ;
+; sign_div_unsign.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/sign_div_unsign.inc ;
+; db/lpm_divide_85m.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/lpm_divide_85m.tdf ;
+; db/sign_div_unsign_fkh.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/sign_div_unsign_fkh.tdf ;
+; db/alt_u_div_00f.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf ;
+; db/add_sub_lkc.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_lkc.tdf ;
+; db/add_sub_mkc.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_mkc.tdf ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+-----------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+-----------------------------------------+
+; Estimated Total logic elements ; 73 ;
+; ; ;
+; Total combinational functions ; 73 ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 11 ;
+; -- 3 input functions ; 23 ;
+; -- <=2 input functions ; 39 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 56 ;
+; -- arithmetic mode ; 17 ;
+; ; ;
+; Total registers ; 16 ;
+; -- Dedicated logic registers ; 16 ;
+; -- I/O registers ; 0 ;
+; ; ;
+; I/O pins ; 0 ;
+; Total PLLs ; 1 ;
+; Maximum fan-out node ; pll:inst1|altpll:altpll_component|_clk0 ;
+; Maximum fan-out ; 16 ;
+; Total fan-out ; 233 ;
+; Average fan-out ; 2.33 ;
++---------------------------------------------+-----------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
++-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------+
+; |demo_top ; 73 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top ;
+; |demo:inst| ; 73 (37) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst ;
+; |lpm_divide:Mod0| ; 36 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0 ;
+; |lpm_divide_85m:auto_generated| ; 36 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated ;
+; |sign_div_unsign_fkh:divider| ; 36 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider ;
+; |alt_u_div_00f:divider| ; 36 (36) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider ;
+; |pll:inst1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|pll:inst1 ;
+; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|pll:inst1|altpll:altpll_component ;
++-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 16 ;
+; Number of registers using Synchronous Clear ; 13 ;
+; Number of registers using Synchronous Load ; 3 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 0 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
+; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |demo_top|demo:inst|knightlight[7] ;
+; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |demo_top|demo:inst|knightlight[2] ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: pll:inst1|altpll:altpll_component ;
++-------------------------------+-------------------+----------------------------+
+; Parameter Name ; Value ; Type ;
++-------------------------------+-------------------+----------------------------+
+; OPERATION_MODE ; NORMAL ; Untyped ;
+; PLL_TYPE ; AUTO ; Untyped ;
+; QUALIFY_CONF_DONE ; OFF ; Untyped ;
+; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
+; SCAN_CHAIN ; LONG ; Untyped ;
+; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
+; INCLK0_INPUT_FREQUENCY ; 40000 ; Signed Integer ;
+; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
+; GATE_LOCK_SIGNAL ; NO ; Untyped ;
+; GATE_LOCK_COUNTER ; 0 ; Untyped ;
+; LOCK_HIGH ; 1 ; Untyped ;
+; LOCK_LOW ; 1 ; Untyped ;
+; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
+; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
+; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
+; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
+; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
+; SKIP_VCO ; OFF ; Untyped ;
+; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
+; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
+; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
+; BANDWIDTH ; 0 ; Untyped ;
+; BANDWIDTH_TYPE ; AUTO ; Untyped ;
+; SPREAD_FREQUENCY ; 0 ; Untyped ;
+; DOWN_SPREAD ; 0 ; Untyped ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
+; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
+; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK1_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK0_MULTIPLY_BY ; 4 ; Signed Integer ;
+; CLK9_DIVIDE_BY ; 0 ; Untyped ;
+; CLK8_DIVIDE_BY ; 0 ; Untyped ;
+; CLK7_DIVIDE_BY ; 0 ; Untyped ;
+; CLK6_DIVIDE_BY ; 0 ; Untyped ;
+; CLK5_DIVIDE_BY ; 1 ; Untyped ;
+; CLK4_DIVIDE_BY ; 1 ; Untyped ;
+; CLK3_DIVIDE_BY ; 1 ; Untyped ;
+; CLK2_DIVIDE_BY ; 1 ; Untyped ;
+; CLK1_DIVIDE_BY ; 1 ; Untyped ;
+; CLK0_DIVIDE_BY ; 1 ; Signed Integer ;
+; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK5_TIME_DELAY ; 0 ; Untyped ;
+; CLK4_TIME_DELAY ; 0 ; Untyped ;
+; CLK3_TIME_DELAY ; 0 ; Untyped ;
+; CLK2_TIME_DELAY ; 0 ; Untyped ;
+; CLK1_TIME_DELAY ; 0 ; Untyped ;
+; CLK0_TIME_DELAY ; 0 ; Untyped ;
+; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
+; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
+; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
+; VCO_MULTIPLY_BY ; 0 ; Untyped ;
+; VCO_DIVIDE_BY ; 0 ; Untyped ;
+; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
+; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
+; VCO_MIN ; 0 ; Untyped ;
+; VCO_MAX ; 0 ; Untyped ;
+; VCO_CENTER ; 0 ; Untyped ;
+; PFD_MIN ; 0 ; Untyped ;
+; PFD_MAX ; 0 ; Untyped ;
+; M_INITIAL ; 0 ; Untyped ;
+; M ; 0 ; Untyped ;
+; N ; 1 ; Untyped ;
+; M2 ; 1 ; Untyped ;
+; N2 ; 1 ; Untyped ;
+; SS ; 1 ; Untyped ;
+; C0_HIGH ; 0 ; Untyped ;
+; C1_HIGH ; 0 ; Untyped ;
+; C2_HIGH ; 0 ; Untyped ;
+; C3_HIGH ; 0 ; Untyped ;
+; C4_HIGH ; 0 ; Untyped ;
+; C5_HIGH ; 0 ; Untyped ;
+; C6_HIGH ; 0 ; Untyped ;
+; C7_HIGH ; 0 ; Untyped ;
+; C8_HIGH ; 0 ; Untyped ;
+; C9_HIGH ; 0 ; Untyped ;
+; C0_LOW ; 0 ; Untyped ;
+; C1_LOW ; 0 ; Untyped ;
+; C2_LOW ; 0 ; Untyped ;
+; C3_LOW ; 0 ; Untyped ;
+; C4_LOW ; 0 ; Untyped ;
+; C5_LOW ; 0 ; Untyped ;
+; C6_LOW ; 0 ; Untyped ;
+; C7_LOW ; 0 ; Untyped ;
+; C8_LOW ; 0 ; Untyped ;
+; C9_LOW ; 0 ; Untyped ;
+; C0_INITIAL ; 0 ; Untyped ;
+; C1_INITIAL ; 0 ; Untyped ;
+; C2_INITIAL ; 0 ; Untyped ;
+; C3_INITIAL ; 0 ; Untyped ;
+; C4_INITIAL ; 0 ; Untyped ;
+; C5_INITIAL ; 0 ; Untyped ;
+; C6_INITIAL ; 0 ; Untyped ;
+; C7_INITIAL ; 0 ; Untyped ;
+; C8_INITIAL ; 0 ; Untyped ;
+; C9_INITIAL ; 0 ; Untyped ;
+; C0_MODE ; BYPASS ; Untyped ;
+; C1_MODE ; BYPASS ; Untyped ;
+; C2_MODE ; BYPASS ; Untyped ;
+; C3_MODE ; BYPASS ; Untyped ;
+; C4_MODE ; BYPASS ; Untyped ;
+; C5_MODE ; BYPASS ; Untyped ;
+; C6_MODE ; BYPASS ; Untyped ;
+; C7_MODE ; BYPASS ; Untyped ;
+; C8_MODE ; BYPASS ; Untyped ;
+; C9_MODE ; BYPASS ; Untyped ;
+; C0_PH ; 0 ; Untyped ;
+; C1_PH ; 0 ; Untyped ;
+; C2_PH ; 0 ; Untyped ;
+; C3_PH ; 0 ; Untyped ;
+; C4_PH ; 0 ; Untyped ;
+; C5_PH ; 0 ; Untyped ;
+; C6_PH ; 0 ; Untyped ;
+; C7_PH ; 0 ; Untyped ;
+; C8_PH ; 0 ; Untyped ;
+; C9_PH ; 0 ; Untyped ;
+; L0_HIGH ; 1 ; Untyped ;
+; L1_HIGH ; 1 ; Untyped ;
+; G0_HIGH ; 1 ; Untyped ;
+; G1_HIGH ; 1 ; Untyped ;
+; G2_HIGH ; 1 ; Untyped ;
+; G3_HIGH ; 1 ; Untyped ;
+; E0_HIGH ; 1 ; Untyped ;
+; E1_HIGH ; 1 ; Untyped ;
+; E2_HIGH ; 1 ; Untyped ;
+; E3_HIGH ; 1 ; Untyped ;
+; L0_LOW ; 1 ; Untyped ;
+; L1_LOW ; 1 ; Untyped ;
+; G0_LOW ; 1 ; Untyped ;
+; G1_LOW ; 1 ; Untyped ;
+; G2_LOW ; 1 ; Untyped ;
+; G3_LOW ; 1 ; Untyped ;
+; E0_LOW ; 1 ; Untyped ;
+; E1_LOW ; 1 ; Untyped ;
+; E2_LOW ; 1 ; Untyped ;
+; E3_LOW ; 1 ; Untyped ;
+; L0_INITIAL ; 1 ; Untyped ;
+; L1_INITIAL ; 1 ; Untyped ;
+; G0_INITIAL ; 1 ; Untyped ;
+; G1_INITIAL ; 1 ; Untyped ;
+; G2_INITIAL ; 1 ; Untyped ;
+; G3_INITIAL ; 1 ; Untyped ;
+; E0_INITIAL ; 1 ; Untyped ;
+; E1_INITIAL ; 1 ; Untyped ;
+; E2_INITIAL ; 1 ; Untyped ;
+; E3_INITIAL ; 1 ; Untyped ;
+; L0_MODE ; BYPASS ; Untyped ;
+; L1_MODE ; BYPASS ; Untyped ;
+; G0_MODE ; BYPASS ; Untyped ;
+; G1_MODE ; BYPASS ; Untyped ;
+; G2_MODE ; BYPASS ; Untyped ;
+; G3_MODE ; BYPASS ; Untyped ;
+; E0_MODE ; BYPASS ; Untyped ;
+; E1_MODE ; BYPASS ; Untyped ;
+; E2_MODE ; BYPASS ; Untyped ;
+; E3_MODE ; BYPASS ; Untyped ;
+; L0_PH ; 0 ; Untyped ;
+; L1_PH ; 0 ; Untyped ;
+; G0_PH ; 0 ; Untyped ;
+; G1_PH ; 0 ; Untyped ;
+; G2_PH ; 0 ; Untyped ;
+; G3_PH ; 0 ; Untyped ;
+; E0_PH ; 0 ; Untyped ;
+; E1_PH ; 0 ; Untyped ;
+; E2_PH ; 0 ; Untyped ;
+; E3_PH ; 0 ; Untyped ;
+; M_PH ; 0 ; Untyped ;
+; C1_USE_CASC_IN ; OFF ; Untyped ;
+; C2_USE_CASC_IN ; OFF ; Untyped ;
+; C3_USE_CASC_IN ; OFF ; Untyped ;
+; C4_USE_CASC_IN ; OFF ; Untyped ;
+; C5_USE_CASC_IN ; OFF ; Untyped ;
+; C6_USE_CASC_IN ; OFF ; Untyped ;
+; C7_USE_CASC_IN ; OFF ; Untyped ;
+; C8_USE_CASC_IN ; OFF ; Untyped ;
+; C9_USE_CASC_IN ; OFF ; Untyped ;
+; CLK0_COUNTER ; G0 ; Untyped ;
+; CLK1_COUNTER ; G0 ; Untyped ;
+; CLK2_COUNTER ; G0 ; Untyped ;
+; CLK3_COUNTER ; G0 ; Untyped ;
+; CLK4_COUNTER ; G0 ; Untyped ;
+; CLK5_COUNTER ; G0 ; Untyped ;
+; L0_TIME_DELAY ; 0 ; Untyped ;
+; L1_TIME_DELAY ; 0 ; Untyped ;
+; G0_TIME_DELAY ; 0 ; Untyped ;
+; G1_TIME_DELAY ; 0 ; Untyped ;
+; G2_TIME_DELAY ; 0 ; Untyped ;
+; G3_TIME_DELAY ; 0 ; Untyped ;
+; E0_TIME_DELAY ; 0 ; Untyped ;
+; E1_TIME_DELAY ; 0 ; Untyped ;
+; E2_TIME_DELAY ; 0 ; Untyped ;
+; E3_TIME_DELAY ; 0 ; Untyped ;
+; M_TIME_DELAY ; 0 ; Untyped ;
+; N_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK3_COUNTER ; E3 ; Untyped ;
+; EXTCLK2_COUNTER ; E2 ; Untyped ;
+; EXTCLK1_COUNTER ; E1 ; Untyped ;
+; EXTCLK0_COUNTER ; E0 ; Untyped ;
+; ENABLE0_COUNTER ; L0 ; Untyped ;
+; ENABLE1_COUNTER ; L0 ; Untyped ;
+; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
+; LOOP_FILTER_R ; 1.000000 ; Untyped ;
+; LOOP_FILTER_C ; 5 ; Untyped ;
+; VCO_POST_SCALE ; 0 ; Untyped ;
+; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; INTENDED_DEVICE_FAMILY ; Cyclone II ; Untyped ;
+; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
+; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
+; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
+; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
+; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK0 ; PORT_USED ; Untyped ;
+; PORT_CLK1 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK6 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK7 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK8 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK9 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
+; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
+; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
+; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
+; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
+; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
+; PORT_INCLK0 ; PORT_USED ; Untyped ;
+; PORT_FBIN ; PORT_UNUSED ; Untyped ;
+; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
+; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
+; PORT_ARESET ; PORT_UNUSED ; Untyped ;
+; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
+; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
+; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
+; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
+; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
+; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
+; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
+; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
+; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
+; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
+; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
+; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
+; M_TEST_SOURCE ; 5 ; Untyped ;
+; C0_TEST_SOURCE ; 5 ; Untyped ;
+; C1_TEST_SOURCE ; 5 ; Untyped ;
+; C2_TEST_SOURCE ; 5 ; Untyped ;
+; C3_TEST_SOURCE ; 5 ; Untyped ;
+; C4_TEST_SOURCE ; 5 ; Untyped ;
+; C5_TEST_SOURCE ; 5 ; Untyped ;
+; C6_TEST_SOURCE ; 0 ; Untyped ;
+; C7_TEST_SOURCE ; 0 ; Untyped ;
+; C8_TEST_SOURCE ; 0 ; Untyped ;
+; C9_TEST_SOURCE ; 0 ; Untyped ;
+; CBXI_PARAMETER ; NOTHING ; Untyped ;
+; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
+; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
+; WIDTH_CLOCK ; 6 ; Untyped ;
+; DEVICE_FAMILY ; Cyclone II ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
++-------------------------------+-------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: demo:inst|lpm_divide:Mod0 ;
++------------------------+----------------+----------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------+----------------+----------------------------------+
+; LPM_WIDTHN ; 8 ; Untyped ;
+; LPM_WIDTHD ; 8 ; Untyped ;
+; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
+; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
+; LPM_PIPELINE ; 0 ; Untyped ;
+; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
+; MAXIMIZE_SPEED ; 5 ; Untyped ;
+; CBXI_PARAMETER ; lpm_divide_85m ; Untyped ;
+; CARRY_CHAIN ; MANUAL ; Untyped ;
+; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
++------------------------+----------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:52:35 2009
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off demo -c demo
+Info: Found 1 design units, including 0 entities, in source file ../src/demo_pkg.vhd
+ Info: Found design unit 1: demo_pkg
+Info: Found 2 design units, including 1 entities, in source file ../src/demo.vhd
+ Info: Found design unit 1: demo-behav
+ Info: Found entity 1: demo
+Info: Found 2 design units, including 1 entities, in source file ../src/pll.vhd
+ Info: Found design unit 1: pll-SYN
+ Info: Found entity 1: pll
+Info: Found 1 design units, including 1 entities, in source file ../src/demo_top.bdf
+ Info: Found entity 1: demo_top
+Info: Elaborating entity "demo_top" for the top level hierarchy
+Info: Elaborating entity "demo" for hierarchy "demo:inst"
+Info: Elaborating entity "pll" for hierarchy "pll:inst1"
+Info: Found 1 design units, including 1 entities, in source file /opt/quartus/libraries/megafunctions/altpll.tdf
+ Info: Found entity 1: altpll
+Info: Elaborating entity "altpll" for hierarchy "pll:inst1|altpll:altpll_component"
+Info: Elaborated megafunction instantiation "pll:inst1|altpll:altpll_component"
+Info: Found 1 design units, including 1 entities, in source file /opt/quartus/libraries/megafunctions/lpm_divide.tdf
+ Info: Found entity 1: lpm_divide
+Info: Elaborated megafunction instantiation "demo:inst|lpm_divide:Mod0"
+Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_85m.tdf
+ Info: Found entity 1: lpm_divide_85m
+Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_fkh.tdf
+ Info: Found entity 1: sign_div_unsign_fkh
+Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_00f.tdf
+ Info: Found entity 1: alt_u_div_00f
+Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
+ Info: Found entity 1: add_sub_lkc
+Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
+ Info: Found entity 1: add_sub_mkc
+Info: Found the following redundant logic cells in design
+ Info: Logic cell "demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[0]~34"
+Info: Implemented 84 device resources after synthesis - the final resource count might be different
+ Info: Implemented 2 input pins
+ Info: Implemented 8 output pins
+ Info: Implemented 73 logic cells
+ Info: Implemented 1 ClockLock PLLs
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
+ Info: Processing ended: Mon Mar 30 19:52:38 2009
+ Info: Elapsed time: 00:00:03
+
+
projects / hwmod.git / blobdiff