--- /dev/null
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:52:45 2009
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off demo -c demo
+Info: Selected device EP2C35F484C6 for design "demo"
+Info: Implemented PLL "pll:inst1|altpll:altpll_component|pll" as Cyclone II PLL type
+ Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:inst1|altpll:altpll_component|_clk0 port
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info: Fitter is using the Classic Timing Analyzer
+Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
+Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
+ Info: Previous placement does not exist for 92 of 92 atoms in partition Top
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP2C15AF484C6 is compatible
+ Info: Device EP2C20F484C6 is compatible
+ Info: Device EP2C50F484C6 is compatible
+Info: Fitter converted 3 user pins into dedicated programming pins
+ Info: Pin ~ASDO~ is reserved at location C4
+ Info: Pin ~nCSO~ is reserved at location C3
+ Info: Pin ~LVDS150p/nCEO~ is reserved at location W20
+Info: Automatically promoted node pll:inst1|altpll:altpll_component|_clk0 (placed in counter C0 of PLL_1)
+ Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
+Info: Starting register packing
+Info: Finished register packing: elapsed time is 00:00:01
+ Extra Info: No registers were packed into other blocks
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:00
+Info: Estimated most critical path is register to register delay of 6.881 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X57_Y31; Fanout = 3; REG Node = 'demo:inst|counter[3]'
+ Info: 2: + IC(0.914 ns) + CELL(0.414 ns) = 1.328 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|Add0~101'
+ Info: 3: + IC(0.000 ns) + CELL(0.410 ns) = 1.738 ns; Loc. = LAB_X55_Y31; Fanout = 3; COMB Node = 'demo:inst|Add0~102'
+ Info: 4: + IC(0.397 ns) + CELL(0.414 ns) = 2.549 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19'
+ Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.620 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21'
+ Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.691 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23'
+ Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.762 ns; Loc. = LAB_X55_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25'
+ Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 3.172 ns; Loc. = LAB_X55_Y31; Fanout = 14; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26'
+ Info: 9: + IC(0.587 ns) + CELL(0.437 ns) = 4.196 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22'
+ Info: 10: + IC(0.397 ns) + CELL(0.414 ns) = 5.007 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21'
+ Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 5.078 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23'
+ Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 5.149 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25'
+ Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 5.220 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27'
+ Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 5.291 ns; Loc. = LAB_X57_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29'
+ Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 5.362 ns; Loc. = LAB_X57_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31'
+ Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 5.772 ns; Loc. = LAB_X57_Y31; Fanout = 7; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32'
+ Info: 17: + IC(0.875 ns) + CELL(0.150 ns) = 6.797 ns; Loc. = LAB_X55_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636'
+ Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 6.881 ns; Loc. = LAB_X55_Y31; Fanout = 3; REG Node = 'demo:inst|counter[1]'
+ Info: Total cell delay = 3.711 ns ( 53.93 % )
+ Info: Total interconnect delay = 3.170 ns ( 46.07 % )
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
+ Info: The peak interconnect region extends from location X22_Y12 to location X32_Y23
+Info: Fitter routing operations ending: elapsed time is 00:00:00
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Started post-fitting delay annotation
+Warning: Found 8 output pins without output pin load capacitance assignment
+ Info: Pin "LEDS[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+Info: Delay annotation completed successfully
+Info: Quartus II Fitter was successful. 0 errors, 1 warning
+ Info: Processing ended: Mon Mar 30 19:52:59 2009
+ Info: Elapsed time: 00:00:14
projects / hwmod.git / blobdiff