--- /dev/null
+EDA Netlist Writer report for demo
+Mon Mar 30 19:53:36 2009
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. EDA Netlist Writer Summary
+ 3. Simulation Settings
+ 4. Simulation Generated Files
+ 5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Mon Mar 30 19:53:36 2009 ;
+; Revision Name ; demo ;
+; Top-level Entity Name ; demo_top ;
+; Family ; Cyclone II ;
+; Simulation Files Creation ; Successful ;
++---------------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Simulation Settings ;
++--------------------------------------------------------------------------------------------+-----------------+
+; Option ; Setting ;
++--------------------------------------------------------------------------------------------+-----------------+
+; Tool Name ; ModelSim (VHDL) ;
+; Generate netlist for functional simulation only ; Off ;
+; Time scale ; 1 ps ;
+; Truncate long hierarchy paths ; Off ;
+; Map illegal HDL characters ; Off ;
+; Flatten buses into individual nodes ; Off ;
+; Maintain hierarchy ; Off ;
+; Bring out device-wide set/reset signals as ports ; Off ;
+; Enable glitch filtering ; Off ;
+; Do not write top level VHDL entity ; Off ;
+; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ;
+; Architecture name in VHDL output netlist ; structure ;
++--------------------------------------------------------------------------------------------+-----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files ;
++-----------------------------------------------------------------------------------------------------------------+
+; Generated Files ;
++-----------------------------------------------------------------------------------------------------------------+
+; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/demo.vho ;
+; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/demo_vhd.sdo ;
++-----------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II EDA Netlist Writer
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:53:35 2009
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off demo -c demo
+Info: Generated files "demo.vho" and "demo_vhd.sdo" in directory "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
+ Info: Processing ended: Mon Mar 30 19:53:36 2009
+ Info: Elapsed time: 00:00:01
+
+