one place for all my love

[hwmod.git] / demo / quartus / db / demo.hier_info

diff --git a/demo/quartus/db/demo.hier_info b/demo/quartus/db/demo.hier_info
new file mode 100644 (file)
index 0000000..cd731fa
--- /dev/null
+++ b/demo/quartus/db/demo.hier_info
@@ -0,0 +1,119 @@
+|demo_top
+LEDS[0] <= demo:inst.leds[0]
+LEDS[1] <= demo:inst.leds[1]
+LEDS[2] <= demo:inst.leds[2]
+LEDS[3] <= demo:inst.leds[3]
+LEDS[4] <= demo:inst.leds[4]
+LEDS[5] <= demo:inst.leds[5]
+LEDS[6] <= demo:inst.leds[6]
+LEDS[7] <= demo:inst.leds[7]
+CLK => pll:inst1.inclk0
+RESET => demo:inst.reset
+
+
+|demo_top|demo:inst
+clk => counter[0].CLK
+clk => counter[1].CLK
+clk => counter[2].CLK
+clk => counter[3].CLK
+clk => counter[4].CLK
+clk => counter[5].CLK
+clk => counter[6].CLK
+clk => ledstate.CLK
+clk => knightlight[0].CLK
+clk => knightlight[1].CLK
+clk => knightlight[2].CLK
+clk => knightlight[3].CLK
+clk => knightlight[4].CLK
+clk => knightlight[5].CLK
+clk => knightlight[6].CLK
+clk => knightlight[7].CLK
+reset => knightlight~0.OUTPUTSELECT
+reset => knightlight~1.OUTPUTSELECT
+reset => knightlight~2.OUTPUTSELECT
+reset => knightlight~3.OUTPUTSELECT
+reset => knightlight~4.OUTPUTSELECT
+reset => knightlight~5.OUTPUTSELECT
+reset => knightlight~6.OUTPUTSELECT
+reset => knightlight~7.OUTPUTSELECT
+reset => ledstate~0.OUTPUTSELECT
+reset => counter~0.OUTPUTSELECT
+reset => counter~1.OUTPUTSELECT
+reset => counter~2.OUTPUTSELECT
+reset => counter~3.OUTPUTSELECT
+reset => counter~4.OUTPUTSELECT
+reset => counter~5.OUTPUTSELECT
+reset => counter~6.OUTPUTSELECT
+leds[0] <= knightlight[0].DB_MAX_OUTPUT_PORT_TYPE
+leds[1] <= knightlight[1].DB_MAX_OUTPUT_PORT_TYPE
+leds[2] <= knightlight[2].DB_MAX_OUTPUT_PORT_TYPE
+leds[3] <= knightlight[3].DB_MAX_OUTPUT_PORT_TYPE
+leds[4] <= knightlight[4].DB_MAX_OUTPUT_PORT_TYPE
+leds[5] <= knightlight[5].DB_MAX_OUTPUT_PORT_TYPE
+leds[6] <= knightlight[6].DB_MAX_OUTPUT_PORT_TYPE
+leds[7] <= knightlight[7].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|demo_top|pll:inst1
+inclk0 => altpll:altpll_component.inclk[0]
+c0 <= altpll:altpll_component.clk[0]
+
+
+|demo_top|pll:inst1|altpll:altpll_component
+inclk[0] => pll.CLK
+inclk[1] => ~NO_FANOUT~
+fbin => ~NO_FANOUT~
+pllena => ~NO_FANOUT~
+clkswitch => ~NO_FANOUT~
+areset => ~NO_FANOUT~
+pfdena => ~NO_FANOUT~
+clkena[0] => ~NO_FANOUT~
+clkena[1] => ~NO_FANOUT~
+clkena[2] => ~NO_FANOUT~
+clkena[3] => ~NO_FANOUT~
+clkena[4] => ~NO_FANOUT~
+clkena[5] => ~NO_FANOUT~
+extclkena[0] => ~NO_FANOUT~
+extclkena[1] => ~NO_FANOUT~
+extclkena[2] => ~NO_FANOUT~
+extclkena[3] => ~NO_FANOUT~
+scanclk => ~NO_FANOUT~
+scanclkena => ~NO_FANOUT~
+scanaclr => ~NO_FANOUT~
+scanread => ~NO_FANOUT~
+scanwrite => ~NO_FANOUT~
+scandata => ~NO_FANOUT~
+phasecounterselect[0] => ~NO_FANOUT~
+phasecounterselect[1] => ~NO_FANOUT~
+phasecounterselect[2] => ~NO_FANOUT~
+phasecounterselect[3] => ~NO_FANOUT~
+phaseupdown => ~NO_FANOUT~
+phasestep => ~NO_FANOUT~
+configupdate => ~NO_FANOUT~
+clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
+clk[1] <= <GND>
+clk[2] <= <GND>
+clk[3] <= <GND>
+clk[4] <= <GND>
+clk[5] <= <GND>
+extclk[0] <= <GND>
+extclk[1] <= <GND>
+extclk[2] <= <GND>
+extclk[3] <= <GND>
+clkbad[0] <= <GND>
+clkbad[1] <= <GND>
+enable1 <= <GND>
+enable0 <= <GND>
+activeclock <= <GND>
+clkloss <= <GND>
+locked <= <GND>
+scandataout <= <GND>
+scandone <= <GND>
+sclkout0 <= <GND>
+sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
+phasedone <= <GND>
+vcooverrange <= <GND>
+vcounderrange <= <GND>
+fbout <= <GND>
+
+