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[hwmod.git] / demo / quartus / db / add_sub_mkc.tdf

diff --git a/demo/quartus/db/add_sub_mkc.tdf b/demo/quartus/db/add_sub_mkc.tdf
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+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=2 cout dataa datab result
+--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:30:03:03:26:SJ cbx_lpm_add_sub 2006:10:11:06:03:24:SJ cbx_mgl 2006:10:28:00:08:48:SJ cbx_stratix 2006:09:18:18:47:42:SJ cbx_stratixii 2006:10:13:22:01:30:SJ  VERSION_END
+
+
+--  Copyright (C) 1991-2007 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN add_sub_mkc
+( 
+       cout    :       output;
+       dataa[1..0]     :       input;
+       datab[1..0]     :       input;
+       result[1..0]    :       output;
+) 
+VARIABLE 
+       carry_eqn[1..0] : WIRE;
+       cin_wire        : WIRE;
+       datab_node[1..0]        : WIRE;
+       sum_eqn[1..0]   : WIRE;
+
+BEGIN 
+       carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
+       cin_wire = B"1";
+       cout = carry_eqn[1..1];
+       datab_node[] = (! datab[]);
+       result[] = sum_eqn[];
+       sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
+END;
+--VALID FILE