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[dide_16.git]
/
bsp2
/
Designflow
/
ppr
/
download
/
simulation
/
modelsim
/
vga_pll.sft
diff --git a/bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll.sft
b/bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll.sft
new file mode 100644
(file)
index 0000000..
5aed62e
--- /dev/null
+++ b/
bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll.sft
@@ -0,0
+1,4
@@
+set tool_name "ModelSim-Altera (Verilog)"
+set corner_file_list {
+ {{"Slow Model"} {vga_pll.vo vga_pll_v.sdo}}
+}