X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp2%2FDesignflow%2Fppr%2Fdownload%2Fsimulation%2Fmodelsim%2Fvga_pll.sft;fp=bsp2%2FDesignflow%2Fppr%2Fdownload%2Fsimulation%2Fmodelsim%2Fvga_pll.sft;h=5aed62ecf6090e1f889bf2b74a3447bf230cce04;hp=0000000000000000000000000000000000000000;hb=3696caab9416ac54ee349798f4735dd4e7bfe57d;hpb=ca832fa8fadb632cc02e0c14bf378dda2c9db74b

diff --git a/bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll.sft b/bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll.sft
new file mode 100644
index 0000000..5aed62e
--- /dev/null
+++ b/bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll.sft
@@ -0,0 +1,4 @@
+set tool_name "ModelSim-Altera (Verilog)"
+set corner_file_list {
+	{{"Slow Model"} {vga_pll.vo vga_pll_v.sdo}}
+}