--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+# Date created = 15:08:54 December 16, 2010
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# dt_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name DEVICE EP1C12Q240C8
+set_global_assignment -name TOP_LEVEL_ENTITY core_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:08:54 DECEMBER 16, 2010"
+set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx_arc.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/pipeline_tb.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/mem_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decoder_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decoder.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/core_top.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/core_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/common_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/alu_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/alu_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/alu.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/xor_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name MISC_FILE /homes/burban/dt/dt.dpf
+set_location_assignment PIN_166 -to bus_tx
+set_location_assignment PIN_152 -to sys_clk
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
projects / calu.git / blobdiff