uart und extension anbindung

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 585e0e2002a3669e684b848e88490ece053802ab..b47559d59e1e5a51f4528fb51120e4f1118367dc 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -20,7 +20,7 @@ signal wb_reg, wb_reg_nxt : writeback_rec;
 signal ext_uart,ext_timer,ext_gpmp,ext_7seg :  extmod_rec;
 signal ext_uart_out, ext_timer_out, ext_gpmp_out : gp_register_t;
 
-signal sel_nxt, dmem_we, bus_rx, ext_anysel : std_logic;
+signal sel_nxt, dmem_we, ext_anysel : std_logic;
 
 signal calc_mem_res : gp_register_t;
 
@@ -81,13 +81,11 @@ begin
                wb_reg.dmem_write_en <= '0';
                wb_reg.hword <= '0';
                wb_reg.byte_s <= '0';
-               bus_rx <= '1';
                
                wb_reg.byte_en <= (others => '0');
                wb_reg.data <= (others =>'0');
        elsif rising_edge(clk) then
                wb_reg <= wb_reg_nxt;
-               bus_rx <= '1';
        end if;
        
 end process; 
@@ -192,7 +190,7 @@ end process;
 
 
 
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result)
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result, hword, byte_s)
 variable reg_we_v : std_logic;
 variable data_out : gp_register_t;
 begin
@@ -222,7 +220,22 @@ begin
                data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0');
        end if;
        
-       data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); 
+       
+       if wb_reg.hword = '1' or wb_reg.byte_s = '1' then
+               if wb_reg.address(1)='1' then
+                       data_out(hword_t'range) := data_out(data_out'high downto (data_out'length/2));
+               end if;
+               data_out(data_out'high downto (data_out'length/2)) := (others => '0');
+               if byte_s = '1' then
+                       if wb_reg.address(0) = '1' then
+                               data_out(byte_t'range) := data_out(hword_t'high downto (hword_t'length/2));
+                       end if;
+                       data_out(hword_t'high downto (hword_t'length/2)) := (others => '0');
+               end if;
+       end if;
+       
+       
+--     data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); 
        
        if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
                data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
@@ -285,6 +298,7 @@ begin
     when EXT_UART_ADDR => 
        ext_uart.sel <= enable;
                ext_anysel <= enable;
+
 --             ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
 --             ext_uart.data <= ram_data;
 --             ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
@@ -300,6 +314,7 @@ begin
        when EXT_7SEG_ADDR => 
                ext_7seg.sel <= enable;
                ext_anysel <= enable;
+
                -- ext_7seg.wr_en <= wb_regdmem_write_en;
                -- ext_7seg.data <= ram_data;
                -- ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);