added instruction rom/ram switch, added new data signaling bit in uart.

[calu.git] / cpu / src / rom.vhd

diff --git a/cpu/src/rom.vhd b/cpu/src/rom.vhd
index 7de1beb5b7b3150b1606bad6b746e95a060175ac..65e639410b7660ccfdd6f46587afabfb1f8a5d6a 100644 (file)
--- a/cpu/src/rom.vhd
+++ b/cpu/src/rom.vhd
@@ -11,11 +11,7 @@ entity rom is
                --System inputs
                        clk : in std_logic;
                --Input
-                       wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-                       
-                       wr_en : in std_logic;
-                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
-                       
+                       rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);                   
                --Output
                        data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
                );