spartan3e: at least it compiles

[calu.git] / cpu / src / ram_xilinx.vhd

diff --git a/cpu/src/ram_xilinx.vhd b/cpu/src/ram_xilinx.vhd
new file mode 100644 (file)
index 0000000..0166b55
--- /dev/null
+++ b/cpu/src/ram_xilinx.vhd
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity ram_xilinx is
+       generic ( ADDR_WIDTH : integer range 1 to integer'high);
+       port(clk : in std_logic;
+               addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+               be : in std_logic_vector(3 downto 0);
+               we : in std_logic; -- dummy :/
+               wdata : in std_logic_vector(31 downto 0);
+               q : out std_logic_vector(31 downto 0)
+       );
+end;