-- r0 = 0, r1 = 1, r2 = 3, r3 = A
signal ram : RAM_TYPE := (
--- 0 => x"ed2802d0", -- ldi r5, 0x5a;;
--- 1 => x"ed008058", -- ldi r0, 0x100b;;
--- 2 => x"e7a80000", -- stw r5, 0(r0);;
--- 3 => "11101011000000000000000000000010",
+ -- 0 => x"ed2802d0", -- ldi r5, 0x5a;;
+ -- 1 => x"ed010058", -- ldi r0, 0x200b;;
+ -- 2 => x"e7a80000", -- stw r5, 0(r0);;
+ -- 3 => x"e7828000", -- stw r0, 0(r5);;
+ -- 4 => "11101011000000000000000000000010",
--8 => "11100111100010000000000000000000", --stw
-- 0 => "11101101000000000000000000000000", --ldi
process(clk)
begin
if rising_edge(clk) then
- --data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+ -- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
case rd_addr is
when "00000000000" => data_out <= x"ed2802d0"; -- ldi r5, 0x5a;;
- when "00000000001" => data_out <= x"ed008058"; -- ldi r0, 0x100b;;
+ when "00000000001" => data_out <= x"ed010058"; -- ldi r0, 0x200b;;
when "00000000010" => data_out <= x"e7a80000"; -- stw r5, 0(r0);;
when others => data_out <= "11101011000000000000000000000010";
end case;