stw alu

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 6db0659bae58fa5baa8f7ac2a2f20d9db6ddf7ac..1093b1b479a4fa2921e13d4eb150265591cd49f4 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -17,6 +17,8 @@ architecture behaviour of r_w_ram is
                                    2 => "11101101000110000000000000100000", -- r3 = 4
                                    3 => "11100000001000010001100000000000", -- r4 = r2 + r3
                                    4 => "11100010001010100000100000000000", -- r5 = r4 and r1
+                                    5 => "11100111101010100000000000000001", -- stw r5,r4,1
+
                                  others => x"F0000000");
 
 --     signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1