extension: instanziert in tb und toplvlentity sowie in den vsim dofiles

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index d51196b00deb2a3869dd20630babf00b6a31b700..ff8fd608d31130bcc5c5301772251fbcb39c9651 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -4,6 +4,7 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.core_pkg.all;
+use work.extension_pkg.all;
 -------------------------------------------------------------------------------
 -- ENTITY
 -------------------------------------------------------------------------------
@@ -48,6 +49,12 @@ architecture behavior of pipeline_tb is
                  signal hword_pin  : std_logic;
                  signal byte_s_pin : std_logic;
                 signal nop_pin : std_logic;
+               -- extension signals
+               signal ext_gpmp :  extmod_rec;
+               signal pointer : pointer_count;
+               signal dec_in,p_en : std_logic;
+               signal data_out    : gp_register_t;
+               signal pointer_val : gp_register_t;
 
 begin
 
@@ -126,6 +133,22 @@ begin
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 
 
+       gpmp_inst :  extension
+               generic map ('0')
+               port map (
+                       sys_clk_pin,
+                       sys_res_n_pin,
+                       ext_gpmp,
+                       pointer,
+                       dec_in,
+                       p_en,
+                       data_out,
+                       pointer_val
+                       
+               );
+
+
+
        nop_pin <= (alu_jump_bit_pin xor brpr_pin);
 
 -------------------------------------------------------------------------------