interrupt version 1

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index e396a6bd78f74079dde3c37d25edb765f2c4b735..de276a8fc8f305a9cdb46437ca626d3b1a484eb1 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -59,7 +59,7 @@ architecture behavior of pipeline_tb is
                 signal cycle_cnt : integer;
 
                signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
-
+               signal int_req_pin : interrupt_t;
 
 begin
 
@@ -98,7 +98,8 @@ begin
 
                --Data outputs
                        instruction => instruction_pin, --: out instruction_word_t
-                       prog_cnt => prog_cnt
+                       prog_cnt => prog_cnt,
+                       int_req => int_req_pin
                );      
 
        decode_st : decode_stage
@@ -137,7 +138,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3, int_req_pin);