signal gpm_out_pin : gp_register_t;
signal nop_pin : std_logic;
+ signal cycle_cnt : integer;
+
begin
wait for cc/2;
end process CLKGEN;
+
+ cnt : process(sys_clk_pin, sys_res_n_pin)
+
+ begin
+
+ if (sys_res_n_pin = '0') then
+ cycle_cnt <= 0;
+ elsif (sys_clk_pin'event and sys_clk_pin = '1') then
+ cycle_cnt <= cycle_cnt + 1;
+ end if;
+
+ end process cnt;
-------------------------------------------------------------------------------
-- test the design
-------------------------------------------------------------------------------