added instruction rom/ram switch, added new data signaling bit in uart.

[calu.git] / cpu / src / mem_pkg.vhd

diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd
index 2c66fb34d5b60d52f9e9888ea8e63186dd757f43..906f175f8ca9d552899f45225cd24042a05a48fe 100644 (file)
--- a/cpu/src/mem_pkg.vhd
+++ b/cpu/src/mem_pkg.vhd
@@ -52,13 +52,9 @@ package mem_pkg is
                --System inputs
                        clk : in std_logic;
                --Input
-                       wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-                       
-                       wr_en : in std_logic;
-                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
-                       
+                       rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);                   
                --Output
-                       data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
+                       data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
        end component rom;