uart:uart entitiy

[calu.git] / cpu / src / extension_uart_pkg.vhd

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
new file mode 100644 (file)
index 0000000..fb839ff
--- /dev/null
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -0,0 +1,87 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+
+
+package extension_uart_pkg is
+
+constant EXTWORDL : integer := log2c(4);
+constant BYTEADDR : integer := log2c(4);
+constant PCOUNT   : integer := 3;
+constant EXTWORDS : integer := EXTWORDL + BYTEADDR;
+
+subtype ext_addrid_t  is std_logic_vector(gp_register_t'high - EXTWORDS downto 0);
+subtype ext_addr_t    is std_logic_vector((gp_register_t'high-BYTEADDR) downto 0);    
+subtype paddr_t is std_logic_vector(log2c(PCOUNT)-1 downto 0);   
+
+        type extmod_rec is record
+                sel   : std_logic;
+                wr_en : std_logic;
+                byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); 
+                data : gp_register_t;
+                addr : ext_addr_t;     
+        end record; 
+
+
+type status_rec is record
+               zero : std_logic;
+               oflo : std_logic;
+               sign : std_logic;
+               carry : std_logic;
+end record;
+
+constant EXT_7SEG_ADDR:   ext_addrid_t := x"FFFFFFA";
+constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
+constant EXT_TIMER_ADDR:  ext_addrid_t := x"FFFFFFC";
+constant EXT_AC97_ADDR:   ext_addrid_t := x"FFFFFFD";
+constant EXT_UART_ADDR:   ext_addrid_t := x"FFFFFFE";
+constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
+--RS232
+constant UART_WIDTH : integer := 8;
+subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
+--CLKs
+constant CLK_FREQ_MHZ : real := 33.33;
+constant BAUD_RATE : integer := 115200;
+constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
+
+ component extension_uart is
+        --some modules won't need all inputs/outputs
+       generic (
+                       -- active reset value
+                       RESET_VALUE : std_logic
+                       );
+       port(
+               --System inputs
+                       clk :   in std_logic;
+                       reset : in std_logic;
+               -- general extension interface                  
+                       ext_reg  : in extmod_rec;
+                       data_out : out gp_register_t;
+               -- Input
+
+               -- Ouput
+                       bus_tx : out std_logic
+               );
+ end component extension_uart;
+
+component rs232_tx is
+
+       port(
+               --System inputs
+               sys_clk : in std_logic;
+               sys_res_n : in std_logic;
+
+               --Bus
+               bus_tx : out std_logic;
+
+               --From/to sendlogic
+               new_tx_data : in std_logic;
+               tx_data : in uart_data;
+               tx_rdy : out std_logic
+       );
+end component rs232_tx;
+
+end package extension_uart_pkg;