uart und extension anbindung

[calu.git] / cpu / src / extension_uart_pkg.vhd

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index 78512225e9f924fd11f9923207860867d1bb21f3..c7fd32f1093aee6af8222c5cb3e018f67256e4f7 100644 (file)
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -70,7 +70,8 @@ end component rs232_tx;
 component rs232_rx is
        generic (
                -- active reset value
-               RESET_VALUE : std_logic
+               RESET_VALUE : std_logic;
+               SYNC_STAGES : integer range 2 to integer'high
                );
 
        port(
@@ -79,7 +80,7 @@ component rs232_rx is
                sys_res_n : in std_logic;
 
                --Bus
-               bus_rx : in std_logic;
+               bus_rx_unsync : in std_logic;
 
                --To sendlogic
                new_rx_data : out std_logic;