modified: interfaces according to SP operation

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index a7809e51786d9deb457f0458de37d3c2b74e1448..ccbfee3ed7cf7ad62fb31f172cb13d0371d2a406 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -19,6 +19,10 @@ signal psw : status_rec;
                signal ext_gpmp :  extmod_rec;
                signal data_out    : gp_register_t;
 
+signal pval : gp_register_t;
+signal paddr : paddr_t;
+signal pinc, pwr_en : std_logic;
+
 
 
 type exec_internal is record
@@ -35,7 +39,7 @@ begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-         left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, alu_nxt,addr,data);
+         left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, alu_nxt,addr,data, pinc, pwr_en, paddr);
 
 
 
@@ -45,10 +49,13 @@ port map(clk, reset, condition, op_group,
                        clk,
                        reset,
                        ext_gpmp,
-                       data_out,
-                       alu_nxt,
-                       psw
-                       
+                       ext_data_out,
+                       alu_nxt.status,
+                       paddr,
+                       pinc,
+                       pwr_en,
+                       psw,
+                       pval
                );