2nd forward unit - 58MHz with 31bit shift...

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 5979a8b048b917574ddc48f5ac5a6efb3ee51e2f..4d69cee026749452d225597e6c1d981d33d5934f 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -51,14 +51,13 @@ begin
        
 end process;
 
-asyn: process(reset,dec_instr, alu_nxt, psw, reg)
+asyn: process(reset,dec_instr, alu_nxt, psw, reg,left_operand,right_operand)
 begin
 
         condition <= dec_instr.condition;
         op_group <= dec_instr.op_group;
         op_detail <= dec_instr.op_detail;
-        left_operand <= dec_instr.src1;
-        right_operand <= dec_instr.src2;
+        
 
 
         alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0'); 
@@ -78,6 +77,21 @@ begin
 
 end process asyn;
 
+forward: process(regfile_val, reg_we, reg_addr, dec_instr.src1,dec_instr.src2)
+begin
+       left_operand <= dec_instr.src1;
+        right_operand <= dec_instr.src2;
+
+       if reg_we = '1' then
+               if dec_instr.saddr1 = reg_addr then
+                       left_operand <= regfile_val;
+               end if;
+               if (dec_instr.saddr2 = reg_addr)  and  (dec_instr.op_detail(IMM_OPT) = '0') then
+                       right_operand <= regfile_val;
+               end if;
+       end if;
+end process forward;
+
 result <= reg.result;
 result_addr <= reg.res_addr;
 alu_jump <= reg.alu_jump;