use work.common_pkg.all;
-
architecture behav of decode_stage is
signal instr_spl : instruction_rec;
end process;
+-- type dec_op is record
+-- condition : condition_t;
+-- op_group : op_info_t;
+-- op_detail : op_opt_t;
+-- brpr : std_logic;
+--
+-- src1 : gp_register_t;
+-- src2 : gp_register_t;
+--
+-- saddr1 : gp_addr_t;
+-- saddr2 : gp_addr_t;
+--
+-- daddr : gp_addr_t;
+--
+-- end record;
+
+to_alu: process(instr_spl)
+
+begin
+
+
+end process;
+
-- async process: decides between memory and read-through-write buffer on output
output: process(rtw_rec, reg1_mem_data, reg2_mem_data)
rtw_rec_nxt.rtw_reg1 <= '0';
rtw_rec_nxt.rtw_reg2 <= '0';
+ rtw_rec_nxt.immediate <= instr_spl.immediate;
+
if (reg_w_addr = instr_spl.reg_src1_addr) then
rtw_rec_nxt.rtw_reg1 <= '1';
end if;