uart und extension anbindung

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 7ece8f1decf6b0e8768b396012ee180e33c613db..730f6ce7af51d6670b9105f823ac83f2b472a177 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -16,6 +16,7 @@ entity core_top is
 --                     reg_wr_data : out gp_register_t
                  -- uart
                        bus_tx : out std_logic;
+                       bus_rx : in std_logic;
                        
                        sseg0 : out std_logic_vector(0 to 6);
                        sseg1 : out std_logic_vector(0 to 6);
@@ -142,7 +143,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk, sys_res, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3);
 
 
 syn: process(sys_clk, sys_res)