interrupt version 1

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index eafb605135bf9a5dcee5c06f88cfc2bb21e6b563..07da7b24afca2dc4b0a8498ff0a93a5352a8905f 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -65,6 +65,8 @@ architecture behav of core_top is
                 
                 signal sync : std_logic_vector(1 to SYNC_STAGES);
                 signal sys_res_n : std_logic;
+
+                signal int_req : interrupt_t;
                 
                 signal vers, vers_nxt : exec2wb_rec;
 begin
@@ -86,6 +88,7 @@ begin
                        prediction_result => prediction_result_pin, --: in instruction_addr_t;
                        branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+                       int_req => int_req,
 
                --Data outputs
                        instruction => instruction_pin, --: out instruction_word_t
@@ -148,7 +151,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3, int_req);
 
 
 syn: process(sys_clk, sys_res)