prediction_result : in instruction_addr_t;
branch_prediction_bit : in std_logic;
alu_jump_bit : in std_logic;
+ int_req : in interrupt_t;
--Data outputs
instruction : out instruction_word_t;
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
sseg2 : out std_logic_vector(0 to 6);
- sseg3 : out std_logic_vector(0 to 6)
+ sseg3 : out std_logic_vector(0 to 6);
+
+ int_req : out interrupt_t
+
);
end component writeback_stage;