end component decoder;
component execute_stage is
+
generic (
-- active reset value
- RESET_VALUE : std_logic;
+ RESET_VALUE : std_logic
-- active logic value
- LOGIC_ACT : std_logic
+ --LOGIC_ACT : std_logic;
);
port(
--System inputs
clk : in std_logic;
- reset : in std_logic
+ reset : in std_logic;
+ dec_instr : in dec_op;
+
+ --System output
+ result : out gp_register_t;--reg
+ result_addr : out gp_addr_t;--reg
+ addr : out word_t; --memaddr
+ data : out gp_register_t; --mem data --ureg
+ alu_jump : out std_logic;--reg
+ brpr : out std_logic; --reg
+ wr_en : out std_logic;--regop --reg
+ dmem : out std_logic;--memop
+ dmem_write_en : out std_logic;
+ hword : out std_logic;
+ byte_s : out std_logic
);
end component execute_stage;
port(
--System inputs
clk : in std_logic;
- reset : in std_logic
+ reset : in std_logic;
result : in gp_register_t; --reg (alu result or jumpaddr)
result_addr : in gp_addr_t; --reg