end record;\r
\r
subtype status_t is byte_t;\r
- type alu_interal_rec is record\r
- \r
- end record alu_internal_rec;\r
+ --type alu_interal_rec is record\r
+ -- \r
+ --end record alu_internal_rec;\r
\r
type alu_result_rec is record\r
result : gp_register_t;\r
reg_op : std_logic;\r
mem_op : std_logic;\r
\r
+ new_val : std_logic;\r
+ mem_en : std_logic;\r
+ \r
hw_op : std_logic;\r
byte_op : std_logic;\r
sign_xt : std_logic;\r
\r
end record alu_result_rec;\r
\r
- constant SHIFT_WIDTH : integer := log2c(gp_register_t'length);\r
+ constant SHIFT_WIDTH : integer := 1;--log2c(gp_register_t'length);\r
+ \r
+ constant COND_ZERO : condition_t := "0001";\r
+ constant COND_NZERO : condition_t := "0000";\r
+ constant COND_NOFLO : condition_t := "0010";\r
+ constant COND_OFLO : condition_t := "0011";\r
+ constant COND_NCARRY : condition_t := "0100";\r
+ constant COND_CARRY : condition_t := "0101";\r
+ constant COND_NSIGN : condition_t := "0110";\r
+ constant COND_SIGN : condition_t := "0111";\r
+ \r
+ constant COND_ABOVE : condition_t := "1000";\r
+ constant COND_BEQ: condition_t := "1001";\r
+ constant COND_GEQ : condition_t := "1010";\r
+ constant COND_LT : condition_t := "1011";\r
+ constant COND_GT : condition_t := "1100";\r
+ \r
+ constant COND_LEQ : condition_t := "1101";\r
+ constant COND_ALWAYS : condition_t := "1110";\r
+ constant COND_NEVER : condition_t := "1111";\r
\r
function add_oflo(l_neg, r_neg, res_neg : std_logic) return std_logic;\r
- function addsub_op(left_operand, right_operand : gp_register_t; sub, addc : std_logic; alu_result : alu_result_rec) return alu_result_rec;\r
+ -- function addsub_op(left_operand, right_operand : gp_register_t; sub, addc : std_logic; alu_result : alu_result_rec) return alu_result_rec;\r
\r
- function and_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
- function or_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
- function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
+ -- function and_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
+ -- function or_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
+ -- function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
\r
- function shift_op(left_operand, right_operand : gp_register_t; arith,sleft,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec;\r
+ -- function shift_op(left_operand, right_operand : gp_register_t; arith,sleft,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec;\r
\r
\r
end package alu_pkg;\r
(not(l_neg) AND not(r_neg) AND res_neg);\r
end function add_oflo;\r
\r
- function addsub_op(left_operand, right_operand : gp_register_t; sub, addc : std_logic; alu_result : alu_result_rec) return alu_result_rec is\r
- variable alu_result_out : alu_result_rec;\r
- variable complement : gp_register_t;\r
- variable carry_res : unsigned(gp_register_t'length downto 0);\r
- variable tmp_right_operand : unsigned(gp_register_t'length downto 0);\r
- variable oflo1, oflo2, l_neg, r_neg : std_logic;\r
- variable addcarry : unsigned(carry_res'range);\r
- begin\r
- alu_result_out := alu_result;\r
+ -- function addsub_op(left_operand, right_operand : gp_register_t; sub, addc : std_logic; alu_result : alu_result_rec) return alu_result_rec is\r
+ -- variable alu_result_out : alu_result_rec;\r
+ -- variable complement : gp_register_t;\r
+ -- variable carry_res : unsigned(gp_register_t'length downto 0);\r
+ -- variable tmp_right_operand : unsigned(gp_register_t'length downto 0);\r
+ -- variable oflo1, oflo2, l_neg, r_neg : std_logic;\r
+ -- variable addcarry : unsigned(carry_res'range);\r
+ -- begin\r
+ -- alu_result_out := alu_result;\r
\r
- addcarry := (others =>'0');\r
- addcarry(0) := unsigned(alu_result.status.carry and addc);\r
+ -- addcarry := (others =>'0');\r
+ -- addcarry(0) := unsigned(alu_result.status.carry and addc);\r
\r
- complement := inc(not(right_operand));\r
- l_neg := left_operand(gp_register_t'high);\r
+ -- complement := inc(not(right_operand));\r
+ -- l_neg := left_operand(gp_register_t'high);\r
\r
- carry_res := unsigned('0' & left_operand)+addcarry;\r
- oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high));\r
+ -- carry_res := unsigned('0' & left_operand)+addcarry;\r
+ -- oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high));\r
\r
- if sub = '1' then\r
- tmp_right_operand := unsigned('0' & complement);\r
- else\r
- tmp_right_operand := unsigned('0' & right_operand);\r
- end if;\r
+ -- if sub = '1' then\r
+ -- tmp_right_operand := unsigned('0' & complement);\r
+ -- else\r
+ -- tmp_right_operand := unsigned('0' & right_operand);\r
+ -- end if;\r
\r
- l_neg := std_logic_vector(carry_res)(gp_register_t'high);\r
- r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high);\r
+ -- l_neg := std_logic_vector(carry_res)(gp_register_t'high);\r
+ -- r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high);\r
\r
- carry_res := carry_res + tmp_right_operand;\r
- oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high));\r
+ -- carry_res := carry_res + tmp_right_operand;\r
+ -- oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high));\r
\r
\r
- alu_result_out.result := std_logic_vector(carry_res)(gp_register_t'range);\r
- alu_result_out.status.carry := std_logic_vector(carry_res)(carry_res'high);\r
+ -- alu_result_out.result := std_logic_vector(carry_res)(gp_register_t'range);\r
+ -- alu_result_out.status.carry := std_logic_vector(carry_res)(carry_res'high);\r
\r
\r
- alu_result_out.status.carry := oflo1 or oflo2;\r
+ -- alu_result_out.status.carry := oflo1 or oflo2;\r
\r
- --sign will be set globally.\r
- --zero will be set globally.\r
+ -- --sign will be set globally.\r
+ -- --zero will be set globally.\r
\r
- return alu_result_out;\r
- end function addsub_op;\r
+ -- return alu_result_out;\r
+ -- end function addsub_op;\r
\r
- function and_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
- variable alu_result_out : alu_result_rec;\r
- begin\r
- alu_result_out := alu_result;\r
- alu_result_out.result := left_operand and right_operand;\r
- end function and_op;\r
+ -- function and_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
+ -- variable alu_result_out : alu_result_rec;\r
+ -- begin\r
+ -- alu_result_out := alu_result;\r
+ -- alu_result_out.result := left_operand and right_operand;\r
+ -- end function and_op;\r
\r
- function or_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
- variable alu_result_out : alu_result_rec;\r
- begin\r
- alu_result_out := alu_result;\r
- alu_result_out.result := left_operand or right_operand;\r
- end function or_op;\r
+ -- function or_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
+ -- variable alu_result_out : alu_result_rec;\r
+ -- begin\r
+ -- alu_result_out := alu_result;\r
+ -- alu_result_out.result := left_operand or right_operand;\r
+ -- end function or_op;\r
\r
- function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
- variable alu_result_out : alu_result_rec;\r
- begin\r
- alu_result_out := alu_result;\r
- alu_result_out.result := left_operand xor right_operand;\r
- end function xor_op;\r
- \r
- function shift_op(left_operand, right_operand : gp_register_t; arith,rs,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec is\r
- variable alu_result_out : alu_result_rec;\r
- variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);\r
- variable tmp_sb : std_logic;\r
- begin\r
- alu_result_out := alu_result;\r
- \r
- if rs = '1' then\r
- tmp_sb := (carry and alu_result.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));\r
- tmp_shift := bit_vector(tmp_sb & left_operand & alu_result.status.carry);\r
- tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
+ -- function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
+ -- variable alu_result_out : alu_result_rec;\r
+ -- begin\r
+ -- alu_result_out := alu_result;\r
+ -- alu_result_out.result := left_operand xor right_operand;\r
+ -- end function xor_op;\r
+ \r
+ -- function shift_op(left_operand, right_operand : gp_register_t; arith,rs,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec is\r
+ -- variable alu_result_out : alu_result_rec;\r
+ -- variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);\r
+ -- variable tmp_sb : std_logic;\r
+ -- begin\r
+ -- alu_result_out := alu_result;\r
+ \r
+ -- if rs = '1' then\r
+ -- tmp_sb := (carry and alu_result.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));\r
+ -- tmp_shift := bit_vector(tmp_sb & left_operand & alu_result.status.carry);\r
+ -- tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
\r
- alu_result_out.status.carry := std_logic_vector(tmp_shift)(0);\r
- else\r
- tmp_sb := (carry and alu_result.status.carry and not(arith));\r
- tmp_shift := bit_vector(alu_result.status.carry & left_operand & tmp_sb);\r
- tmp_shift := tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
+ -- alu_result_out.status.carry := std_logic_vector(tmp_shift)(0);\r
+ -- else\r
+ -- tmp_sb := (carry and alu_result.status.carry and not(arith));\r
+ -- tmp_shift := bit_vector(alu_result.status.carry & left_operand & tmp_sb);\r
+ -- tmp_shift := tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
\r
- alu_result_out.status.carry := std_logic_vector(tmp_shift)(tmp_shift'high);\r
- end if;\r
+ -- alu_result_out.status.carry := std_logic_vector(tmp_shift)(tmp_shift'high);\r
+ -- end if;\r
\r
- alu_result_out.result := std_logic_vector(tmp_shift)(gp_register_t'length downto 1);\r
+ -- alu_result_out.result := std_logic_vector(tmp_shift)(gp_register_t'length downto 1);\r
\r
- end function shift_op;\r
+ -- end function shift_op;\r
\r
end package body alu_pkg;\r
projects / calu.git / blobdiff