modified: interfaces according to SP operation

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 696e0f798fb647394689a9e147b3e0522f0a3aa4..c46f9e5a926a1bc1ca9dd2bf4d96caf19f5e08e4 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -22,24 +22,24 @@ architecture behaviour of alu is
        end component exec_op;\r
        \r
        signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
-        signal left, right : gp_register_t;\r
+        signal left_o, right_o : gp_register_t;\r
        \r
 begin\r
 \r
        add_inst : entity work.exec_op(add_op)\r
-       port map(clk,reset,left, right, op_detail, alu_state, add_result);\r
+       port map(clk,reset,left_o, right_o, op_detail, alu_state, add_result);\r
        \r
        and_inst : entity work.exec_op(and_op)\r
-       port map(clk,reset,left, right, op_detail, alu_state, and_result);\r
+       port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result);\r
 \r
        or_inst : entity work.exec_op(or_op)\r
-       port map(clk,reset,left, right, op_detail, alu_state, or_result);\r
+       port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result);\r
 \r
        xor_inst : entity work.exec_op(xor_op)\r
-       port map(clk,reset,left, right, op_detail, alu_state, xor_result);\r
+       port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result);\r
        \r
        shift_inst : entity work.exec_op(shift_op)\r
-       port map(clk,reset,left, right, op_detail, alu_state, shift_result);\r
+       port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);\r
 \r
 calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr)\r
        variable result_v : alu_result_rec;\r
@@ -54,11 +54,11 @@ begin
        \r
        res_prod := '1';\r
        mem_en := '0';\r
-        mem_op := '0';\r
+    mem_op := '0';\r
        alu_jump := '0';\r
   \r
-        left <= left_operand;\r
-        right <= right_operand;\r
+        left_o <= left_operand;\r
+        right_o <= right_operand;\r
 \r
         addr <= add_result.result;\r
         data <= right_operand;\r
@@ -124,15 +124,16 @@ begin
                         mem_op := '0';\r
                 end if;\r
                 if op_detail(ST_OPT) = '1' then\r
-                        right <= displacement;\r
+                        right_o <= displacement;\r
                         mem_en := '1';\r
                 end if;\r
        when JMP_OP =>\r
                if op_detail(JMP_REG_OPT) = '0' then\r
-                       left <= prog_cnt;\r
+                       left_o <= prog_cnt;\r
                end if;\r
                alu_jump := '1';\r
        when JMP_ST_OP => null;\r
+               \r
        end case;\r
        \r
 \r
@@ -149,7 +150,7 @@ begin
        \r
        result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
        result_v.mem_en := mem_en and cond_met;\r
-        result_v.mem_op := mem_op and cond_met;\r
+    result_v.mem_op := mem_op and cond_met;\r
        result_v.alu_jump := alu_jump and cond_met;\r
        result_v.brpr := brpr and nop;\r
         \r