fix dell s1850, ROMCC didn't seem to like SSE2 memtest here.
authorStefan Reinauer <stepan@coresystems.de>
Wed, 17 Mar 2010 02:09:12 +0000 (02:09 +0000)
committerStefan Reinauer <stepan@openbios.org>
Wed, 17 Mar 2010 02:09:12 +0000 (02:09 +0000)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/intel/model_f0x/Kconfig
src/cpu/intel/model_f1x/Kconfig
src/cpu/intel/model_f2x/Kconfig
src/cpu/intel/model_f3x/Kconfig
src/cpu/intel/model_f4x/Kconfig
src/cpu/intel/socket_mPGA604/Kconfig
src/mainboard/dell/s1850/Kconfig
src/southbridge/intel/i82801ex/i82801ex_watchdog.c

index bf26cfe04815fc5cc1d40aa9011786e619074a67..9dd7fd0bdccf34ba742f694140e01db94174a003 100644 (file)
@@ -1,4 +1,3 @@
 config CPU_INTEL_MODEL_F0X
        bool
        select SMP
-       select SSE2
index 328930cb8c243b517a5d43425f9593b91b90ae81..ea7585794957dbf79af460f4adfbe80ce41637b9 100644 (file)
@@ -1,4 +1,3 @@
 config CPU_INTEL_MODEL_F1X
        bool
        select SMP
-       select SSE2
index 1672fda7e920509fbe0fe53b70b4bfc7a48f045c..50cac7937cdb0a487f9d1806aa54ec7c2ef3acb4 100644 (file)
@@ -1,4 +1,3 @@
 config CPU_INTEL_MODEL_F2X
        bool
        select SMP
-       select SSE2
index 1a2fa36922ccddb2c5afa12d5e8c7d1c0d1deaf7..4cfca83dc66ffd1dc6845277b8736f5445822c53 100644 (file)
@@ -1,4 +1,3 @@
 config CPU_INTEL_MODEL_F3X
        bool
        select SMP
-       select SSE2
index e765e335d69021084608266a5efff33b97ffdf10..97c909a0ae2d87c9285906b27b43110e64cea48b 100644 (file)
@@ -1,4 +1,3 @@
 config CPU_INTEL_MODEL_F4X
        bool
        select SMP
-       select SSE2
index 2668174e719f37c80405b10c059b35cdae883c58..faa74d33902d9123c1d0b0b45e25d30a56d41bd2 100644 (file)
@@ -6,3 +6,11 @@ config CPU_INTEL_SOCKET_MPGA604
        select MMX
        select SSE
        select UDELAY_TSC
+
+# mPGA604 are usually Intel Netburst CPUs which should have SSE2
+# but the ramtest.c code on the Dell S1850 seems to choke on 
+# enabling it, so disable it for now.
+config SSE2
+       bool
+       default n
+       depends on CPU_INTEL_SOCKET_MPGA604
index 853e2ab7a5cb55a8175d3075eeeb22ba69923303..112abb54c1557284577cd0fde2b8c9ed9879f73f 100644 (file)
@@ -11,6 +11,7 @@ config BOARD_DELL_S1850
        select BOARD_HAS_HARD_RESET
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
+       select USE_WATCHDOG_ON_BOOT
        select BOARD_ROMSIZE_KB_1024
        select UDELAY_TSC
 
index c9c09f5896d49a2000eafb65bfcbe27bef60e848..44a701823a3a8433b42549c661973dadba3dc141 100644 (file)
@@ -1,4 +1,5 @@
 #include <console/console.h>
+#include <watchdog.h>
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>