Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5237
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
config CPU_INTEL_MODEL_F0X
bool
select SMP
- select SSE2
config CPU_INTEL_MODEL_F1X
bool
select SMP
- select SSE2
config CPU_INTEL_MODEL_F2X
bool
select SMP
- select SSE2
config CPU_INTEL_MODEL_F3X
bool
select SMP
- select SSE2
config CPU_INTEL_MODEL_F4X
bool
select SMP
- select SSE2
select MMX
select SSE
select UDELAY_TSC
+
+# mPGA604 are usually Intel Netburst CPUs which should have SSE2
+# but the ramtest.c code on the Dell S1850 seems to choke on
+# enabling it, so disable it for now.
+config SSE2
+ bool
+ default n
+ depends on CPU_INTEL_SOCKET_MPGA604
select BOARD_HAS_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
+ select USE_WATCHDOG_ON_BOOT
select BOARD_ROMSIZE_KB_1024
select UDELAY_TSC
#include <console/console.h>
+#include <watchdog.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>