architecture sim of beh_uart_tx_tb is
- constant clk_period : time := 10ns;
+ constant clk_period : time := 2ns;
signal clock : std_logic;
signal reset : std_logic;
signal done : std_logic;
signal newsig : std_logic;
+ signal data : std_logic_vector(7 downto 0);
+ signal serial_out : std_logic;
begin
inst : entity work.uart_tx(beh)
port map (
- sys_clk => clock,
- sys_res => reset,
- --=> txd,
- --=> tx_data,
- tx_new => newsig,
- tx_done => done
+ sys_clk => clock,
+ sys_res => reset,
+ txd => serial_out,
+ tx_data => data,
+ tx_new => newsig,
+ tx_done => done
);
stimuli : process
newsig <= '0';
wait for 10ns;
--send 'Hallo Welt'
+ data <= X"42";
newsig <= '1';
wait for 1000ns;
port(
sys_clk : in std_logic;
sys_res : in std_logic;
- --txd : out std_logic;
- --tx_data : in std_logic;
+ txd : out std_logic;
+ tx_data : in std_logic_vector(7 downto 0); -- map this to a larger register with containing input
tx_new : in std_logic;
tx_done : out std_logic
);
signal timer : integer range 0 to 65535;
signal timer_next : integer range 0 to 65535;
constant timer_max : integer := 35;
- signal counter : integer;
- signal counter_next : integer;
+ signal counter : integer range 0 to 15;
+ signal counter_next : integer range 0 to 15;
+ signal txd_next : std_logic;
begin
process (sys_clk, sys_res)
begin
if sys_res = '0' then
counter <= 0;
timer <= 0;
+ txd <= '0';
+ txd_next <= '0';
elsif rising_edge(sys_clk) then
counter <= counter_next;
timer <= timer_next;
+ txd <= txd_next;
end if;
end process;
-
- process (timer, counter)
+ process(timer)
begin
if (timer = timer_max) then
timer_next <= 0;
- counter_next <= counter + 1;
else
timer_next <= timer + 1;
- counter_next <= counter;
end if;
end process;
+ process (timer, counter, tx_new)
+ begin
+ if (tx_new = '1') then
+ if (timer = timer_max) then
+ if (counter > 10) then
+ counter_next <= 0;
+ else
+ counter_next <= counter + 1;
+ end if;
+ else
+ counter_next <= counter;
+ end if;
+ else
+ counter_next <= 0;
+ end if;
+ end process;
+
+ process (counter)
+ begin
+ -- TODO: this is always 8N1 and anything but optimal
+ case (counter) is
+ when 0 =>
+ txd_next <= '1';
+ when 1 =>
+ txd_next <= tx_data(0);
+ when 2 =>
+ txd_next <= tx_data(1);
+ when 3 =>
+ txd_next <= tx_data(2);
+ when 4 =>
+ txd_next <= tx_data(3);
+ when 5 =>
+ txd_next <= tx_data(4);
+ when 6 =>
+ txd_next <= tx_data(5);
+ when 7 =>
+ txd_next <= tx_data(6);
+ when 8 =>
+ txd_next <= tx_data(7);
+ when 9 =>
+ txd_next <= '0';
+ when 10 =>
+ txd_next <= '1';
+ when others =>
+ txd_next <= '1';
+ end case;
+ end process;
+
tx_done <= '0';
end architecture beh;