Move the SET_FIDVID* family of configuration options to Kconfig and

make their defaults more obvious.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 3789fdebdf589adecb128660f229770adaade3e1..5ec6b270c0cf1c70c7821a76189522e9239a5757 100644 (file)
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -4,27 +4,50 @@ config CPU_AMD_MODEL_10XXX
        select SSE
        select SSE2
 
+if CPU_AMD_MODEL_10XXX
 config CPU_ADDR_BITS
        int
        default 48
-       depends on CPU_AMD_MODEL_10XXX
 
 config DCACHE_RAM_BASE
        hex
        default 0xc4000
-       depends on CPU_AMD_MODEL_10XXX
 
 config DCACHE_RAM_SIZE
        hex
        default 0x0c000
-       depends on CPU_AMD_MODEL_10XXX
 
 config DCACHE_RAM_GLOBAL_VAR_SIZE
        hex
        default 0x04000
-       depends on CPU_AMD_MODEL_10XXX
 
 config UDELAY_IO
        bool
        default n
-       depends on CPU_AMD_MODEL_10XXX
+
+config SET_FIDVID
+       bool
+       default y
+
+if SET_FIDVID
+config SET_FIDVID_DEBUG
+       bool
+       default y
+
+config SET_FIDVID_STORE_AP_APICID_AT_FIRST
+       bool
+       default y
+
+config SET_FIDVID_CORE0_ONLY
+       bool
+       default n
+
+# 0: all cores
+# 1: core 0 only
+# 2: all but core 0
+config SET_FIDVID_CORE_RANGE
+       int
+       default 0
+
+endif
+endif

diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index 22295c5654e3966179bf298febf9be4135bd95c7..b1a064a8691746502a0b626cc495e57bf9c061ee 100644 (file)
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -17,31 +17,26 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 #include <northbridge/amd/amdht/AsPsDefs.h>
 
-#define SET_FIDVID_DEBUG 1
-
-// if we are tight of CAR stack, disable it
-#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
-
 static inline void print_debug_fv(const char *str, u32 val)
 {
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
        printk(BIOS_DEBUG, "%s%x\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_8(const char *str, u8 val)
 {
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
        printk(BIOS_DEBUG, "%s%02x\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
 {
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
        printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
 #endif
 }
@@ -729,7 +724,7 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid)
 }
 
 
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
 struct ap_apicid_st {
        u32 num;
        // it could use 256 bytes for 64 node quad core system
@@ -748,7 +743,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp)
 
 static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
 {
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
        struct ap_apicid_st ap_apicidx;
        u32 i;
 #endif
@@ -806,20 +801,20 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
        fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8);
        print_debug_fv("BSP fid = ", fv.common_fid);
 
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && SET_FIDVID_CORE0_ONLY == 0
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY
        /* For all APs (We know the APIC ID of all APs even when the APIC ID
           is lifted) remote read from AP LAPIC_MSG_REG about max fid.
           Then calculate the common max fid that can be used for all
           APs and BSP */
        ap_apicidx.num = 0;
 
-       for_each_ap(bsp_apicid, SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
+       for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
 
        for (i = 0; i < ap_apicidx.num; i++) {
                init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
        }
 #else
-       for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
+       for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
 #endif
 
        print_debug_fv("common_fid = ", fv.common_fid);

diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 8f85bceb758b4a64a39eab2a8505e3c55ae6b9b0..0498fea4d4f80123af8253e56349599af43483c6 100644 (file)
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -28,17 +28,6 @@
 #include <cpu/x86/mtrr/earlymtrr.c>
 #include <northbridge/amd/amdfam10/raminit_amdmct.c>
 
-//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
-#ifndef SET_FIDVID
-       #define SET_FIDVID 1
-#endif
-
-#ifndef SET_FIDVID_CORE0_ONLY
-       /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
-          Need to do every AP to set common FID/VID */
-       #define SET_FIDVID_CORE0_ONLY 0
-#endif
-
 static void prep_fid_change(void);
 static void init_fidvid_stage2(u32 apicid, u32 nodeid);
 void cpuSetAMDMSR(void);
@@ -166,7 +155,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
        return result;
 }
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
 #endif
 
@@ -338,8 +327,8 @@ static u32 init_cpus(u32 cpu_init_detectedx)
                update_microcode(cpuid_eax(1));
                cpuSetAMDMSR();
 
-#if SET_FIDVID == 1
-#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1)
+#if CONFIG_SET_FIDVID
+#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY
                // Run on all AP for proper FID/VID setup.
                if (id.coreid == 0)     // only need set fid for core0
 #endif
@@ -928,7 +917,7 @@ static void finalize_node_setup(struct sys_info *sysinfo)
                cpuSetAMDPCI(i);
        }
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        // Prep each node for FID/VID setup.
        prep_fid_change();
 #endif

diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig
index 139b96ad250f4b9cadbcbeb5be173ae1d42ce2f8..962b399e03dff409abf0b74f825881b11cd39a65 100644 (file)
--- a/src/cpu/amd/model_fxx/Kconfig
+++ b/src/cpu/amd/model_fxx/Kconfig
@@ -4,7 +4,31 @@ config CPU_AMD_MODEL_FXX
        select SSE
        select SSE2
 
+if CPU_AMD_MODEL_FXX
 config UDELAY_IO
        bool
        default n
-       depends on CPU_AMD_MODEL_FXX
+
+config SET_FIDVID
+       bool
+       default n
+       default y if K8_REV_F_SUPPORT
+
+if SET_FIDVID
+config SET_FIDVID_DEBUG
+       bool
+       default n
+
+config SET_FIDVID_CORE0_ONLY
+       bool
+       default y
+
+config SET_FIDVID_ONE_BY_ONE
+       bool
+       default y
+
+config SET_FIDVID_STORE_AP_APICID_AT_FIRST
+       bool
+       default y
+endif
+endif

diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c
index bfbc93d577da1f7e03627ea20a51e2df7452e9fc..bbafde666227f0973bc5c46e8f5fb7e202f8de17 100644 (file)
--- a/src/cpu/amd/model_fxx/fidvid.c
+++ b/src/cpu/amd/model_fxx/fidvid.c
@@ -1,10 +1,4 @@
-#if SET_FIDVID == 1
-
-#define SET_FIDVID_DEBUG 0
-
-#define SET_FIDVID_ONE_BY_ONE 1
-
-#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
+#if CONFIG_SET_FIDVID
 
 #ifndef SB_VFSMAF
 #define SB_VFSMAF 1
@@ -14,21 +8,21 @@
 
 static inline void print_debug_fv(const char *str, u32 val)
 {
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
        printk(BIOS_DEBUG, "%s%x\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_8(const char *str, u8 val)
 {
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
        printk(BIOS_DEBUG, "%s%02x\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
 {
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
        printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
 #endif
 }
@@ -70,7 +64,7 @@ static void enable_fid_change(void)
        }
 }
 
-#if SET_FIDVID_ONE_BY_ONE == 0
+#if !CONFIG_SET_FIDVID_ONE_BY_ONE
 static unsigned set_fidvid_without_init(unsigned fidvid)
 {
        msr_t msr;
@@ -276,7 +270,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
                ldtstop_sb();
 #endif
 
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
                if (showmessage) {
                        print_debug_fv_8("set_fidvid APICID = ", apicid);
                        print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo);
@@ -290,7 +284,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
                }
                fid_cur = msr.lo & 0x3f;
 
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
                if (showmessage) {
                        print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo);
                }
@@ -368,7 +362,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
        send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16;   /* max vid */
        send |= (apicid << 24); /* ap apicid */
 
-#if SET_FIDVID_ONE_BY_ONE == 1
+#if CONFIG_SET_FIDVID_ONE_BY_ONE
        vid_cur = msr.hi & 0x3f;
        fid_cur = msr.lo & 0x3f;
 
@@ -399,7 +393,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
        }
 
        if (loop > 0) {
-#if SET_FIDVID_ONE_BY_ONE == 1
+#if CONFIG_SET_FIDVID_ONE_BY_ONE
                readback = set_fidvid(apicid, readback & 0xffff00, 1);  // this AP
 #else
                readback = set_fidvid_without_init(readback & 0xffff00);        // this AP
@@ -502,7 +496,7 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp)
        print_debug_fv("\treadback=", readback);
 }
 
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
 struct ap_apicid_st {
        u32 num;
        unsigned apicid[16];    /* 8 way dual core need 16 */
@@ -524,7 +518,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
 
        struct fidvid_st fv;
 
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
        struct ap_apicid_st ap_apicidx;
        unsigned i;
 #endif
@@ -551,16 +545,16 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
 
        /* calculate the common max fid/vid that could be used for
         * all APs and BSP */
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
        ap_apicidx.num = 0;
 
-       for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx);
+       for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx);
 
        for (i = 0; i < ap_apicidx.num; i++) {
                init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
        }
 #else
-       for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
+       for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
 #endif
 
 #if 0
@@ -587,7 +581,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
 
 #endif
 
-#if SET_FIDVID_ONE_BY_ONE == 1
+#if CONFIG_SET_FIDVID_ONE_BY_ONE
        /* set BSP fid and vid */
        print_debug_fv("bsp apicid=", bsp_apicid);
        fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
@@ -601,15 +595,15 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
        fv.common_fidvid &= 0xffff00;
 
        /* set state 2 allow is in init_fidvid_bsp_stage2 */
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
        for (i = 0; i < ap_apicidx.num; i++) {
                init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv);
        }
 #else
-       for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv);
+       for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv);
 #endif
 
-#if SET_FIDVID_ONE_BY_ONE == 0
+#if !CONFIG_SET_FIDVID_ONE_BY_ONE
        /* set BSP fid and vid */
        print_debug_fv("bsp apicid=", bsp_apicid);
        fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);

diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 5672a6e8f155990c548bab341cd68e932e2a9531..570cb4e585c875e4c21619e6b80c232fe0da5fd0 100644 (file)
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -2,22 +2,6 @@
 #include "option_table.h"
 #endif
 
-//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
-#ifndef SET_FIDVID
-#if CONFIG_K8_REV_F_SUPPORT == 0
-       #define SET_FIDVID 0
-#else
-               // for rev F, need to set FID to max
-       #define SET_FIDVID 1
-#endif
-
-#endif
-
-#ifndef SET_FIDVID_CORE0_ONLY
-       /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice */
-       #define SET_FIDVID_CORE0_ONLY 1
-#endif
-
 typedef void (*process_ap_t) (u32 apicid, void *gp);
 
 //core_range = 0 : all cores
@@ -135,7 +119,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
 
 #define LAPIC_MSG_REG 0x380
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 static void init_fidvid_ap(u32 bsp_apicid, u32 apicid);
 #endif
 
@@ -291,8 +275,8 @@ static u32 init_cpus(u32 cpu_init_detectedx)
                u32 timeout = 1;
                u32 loop = 100;
 
-#if SET_FIDVID == 1
-#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1)
+#if CONFIG_SET_FIDVID
+#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY
                if (id.coreid == 0)     // only need set fid for core0
 #endif
                        init_fidvid_ap(bsp_apicid, apicid);

diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig
index 8a3e900364c3f1c309791ae83a67bab948f6b07f..d585aac69293bafd107837c47bc1b6b169c09195 100644 (file)
--- a/src/mainboard/amd/dbm690t/Kconfig
+++ b/src/mainboard/amd/dbm690t/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_1024
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 3da0fd52eb4895f85ec706bed8da66c8fc6276e1..89b744b98e1a6aa1ca23832a3d9f9e27680be8fa 100644 (file)
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -17,7 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SET_FIDVID 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig
index 6e2239b5e3de238dafdec4729411e756e34bdd89..4e926d83ce23f072d02e786d2d1539561a643180 100644 (file)
--- a/src/mainboard/amd/mahogany/Kconfig
+++ b/src/mainboard/amd/mahogany/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select RAMINIT_SYSINFO
        select GFXUMA
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 7fb715bc5fe984d98aae1ca598088ffa7e2c9ded..869d28b64ef3df95124a71584e8cbd3a3cf86453 100644 (file)
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -17,7 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SET_FIDVID 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 0c360ff2560fadff22a24b504ccf159a53e4e5c6..49d042fe75dde7394b10d26cb6c1cfb836709140 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -27,10 +27,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -196,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs780_early_setup();
        sb700_early_setup();
 
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig
index 94134584c7d1bae83edbcb4c57d0053cc07c9ba9..b77efb3fdda32820a4e444b5de105fe1c01d434f 100644 (file)
--- a/src/mainboard/amd/pistachio/Kconfig
+++ b/src/mainboard/amd/pistachio/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_1024
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 5e143224788c0b9c1cd47818d8c3f07c4c9e866d..4da287abf13be732d7af5b2f3b55e562991a6240 100644 (file)
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -17,7 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SET_FIDVID 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 69d7dcdaab5fab558974a60bec643bd1181d91ee..b08081b407e850d29e113afb43332c9e80a35d5b 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -1,10 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -150,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         int needs_reset;
         unsigned bsp_apicid = 0;
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        struct cpuid_result cpuid1;
 #endif
 
@@ -214,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 #endif
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        /* Check to see if processor is capable of changing FIDVID  */
        /* otherwise it will throw a GP# when reading FIDVID_STATUS */
        cpuid1 = cpuid(0x80000007);

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index a908913cf4c1d4cae24c0f0a69ec1ed5827f361a..d9491c7498121b0890f859677d33b4f9e9fa24c7 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -27,10 +27,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -195,7 +191,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x38);
 
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 273d7a8b4340ca9b0976ca1a026ed12c964b34ac..3c4606d3cf080bb5097d3cbe6690de530b5b43d6 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -27,10 +27,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -196,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs780_early_setup();
        sb700_early_setup();
 
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig
index e08bf91d97f6df06783cf6125da5c04228188208..79901692dec5888f4ce1e575f92f7eee83f18c91 100644 (file)
--- a/src/mainboard/asrock/939a785gmh/Kconfig
+++ b/src/mainboard/asrock/939a785gmh/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select GFXUMA
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 4e1ee79c03c5d77389c8e4e04a8128615dd42305..d42a6268efba9914e836102164a15115e60397b5 100644 (file)
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SET_FIDVID 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig
index 70caf20cf46047b29f01d8fa2d2601461d25b46c..6f85872dcfd98c293150f4d0f22c085c6ca3ed06 100644 (file)
--- a/src/mainboard/asus/a8v-e_deluxe/Kconfig
+++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig
@@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_512
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 008a345d835c6bd8cc8e500ea89b916a56f4995e..aab0377592d06d77177ff98f8761e8d7cbcde8b8 100644 (file)
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -24,12 +24,6 @@
 
 unsigned int get_sbdn(unsigned bus);
 
-/* Used by init_cpus and fidvid */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>

diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig
index c5d3394cfaf64a7776c605249589c85f356ce3ba..2c0ac0476fcd20d49136ec2539dceed0c0a3c1e4 100644 (file)
--- a/src/mainboard/asus/a8v-e_se/Kconfig
+++ b/src/mainboard/asus/a8v-e_se/Kconfig
@@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_512
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 008a345d835c6bd8cc8e500ea89b916a56f4995e..aab0377592d06d77177ff98f8761e8d7cbcde8b8 100644 (file)
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -24,12 +24,6 @@
 
 unsigned int get_sbdn(unsigned bus);
 
-/* Used by init_cpus and fidvid */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>

diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig
index ea25cb37136cb90bd66c1806e03893f44cf81def..9e3b2649a6cc8924b7d3d6930884d70776724f5f 100644 (file)
--- a/src/mainboard/asus/m2v-mx_se/Kconfig
+++ b/src/mainboard/asus/m2v-mx_se/Kconfig
@@ -37,6 +37,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select TINY_BOOTBLOCK
        select HAVE_MAINBOARD_RESOURCES
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index f252b3d220ff1207b5c91969434209efea75a5f8..91a75adfb8bcbcfe53e5a5243830d982447e19cc 100644 (file)
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -24,12 +24,6 @@
 
 unsigned int get_sbdn(unsigned bus);
 
-/* Used by init_cpus and fidvid */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif

diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig
index 3b405abc41ad56d49e288079cdd3dc25ec68d79b..f842455192081096180d90dc770f53d3cfcd928d 100644 (file)
--- a/src/mainboard/asus/m2v/Kconfig
+++ b/src/mainboard/asus/m2v/Kconfig
@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select HAVE_PIRQ_TABLE
        select HAVE_ACPI_TABLES
        select HAVE_MP_TABLE
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 012ca09a0f5f3eb37ca6c1cca61f2fbc721f9137..80aa43d99fd321f20b0157f3d52b95e5c7a70809 100644 (file)
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -27,10 +27,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -197,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs780_early_setup();
        sb700_early_setup();
 
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
index 395c75e5bc3f257ba5825108df5deeaa2328d4a9..85a89d09e34faf1e23a16bb4edf8b92329a43934 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
        select K8_ALLOCATE_IO_RANGE
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 69d068dd3bbec44e117db351b5cca1722580dff5..d688713e0fd7b6acdde842471799cb189a526651 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -25,11 +25,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -212,7 +207,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 
         {
                 msr_t msr;

diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index db8465ee9321a22e5e727e25dfc50022eba0dcb0..4abe1c874482f404238eabd0f20877ca342d0552 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
        select K8_ALLOCATE_IO_RANGE
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 1045a573abeadb93a1049f54a6204ad7ac4e2432..dd84ebfa188672a08119040b48762547bc611bee 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -23,11 +23,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -223,7 +218,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 
         {
                 msr_t msr;

diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index bca7eb5120f14eec7cc50fc30c46db9f490968f6..8b43f6d613329c3e538258c499c2d256e1df606a 100644 (file)
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -23,10 +23,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -192,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs780_early_setup();
        sb700_early_setup();
 
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index ed8a15e6b18c7f99b22f1569904b7bfaa46e2d74..d21644c721e6bc7408d5eff3cb642b5f6366b49f 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -27,10 +27,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -195,7 +191,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs780_early_setup();
        sb700_early_setup();
 
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig
index b5b75a53f4898993f579549418f62614405fb11d..e4c1aa8d3bc50d77b654857aca8608705c4ac8eb 100644 (file)
--- a/src/mainboard/hp/dl145_g3/Kconfig
+++ b/src/mainboard/hp/dl145_g3/Kconfig
@@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
        select QRANK_DIMM_SUPPORT
        select K8_ALLOCATE_IO_RANGE
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 883ee32a2f634f1d01b02721f7b39c3caa0974bb..330d4a51df1215f0ed5c68850c52c39421df83f5 100644 (file)
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -29,11 +29,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -229,7 +224,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
        bcm5785_early_setup();
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        {
                msr_t msr;
                msr=rdmsr(0xc0010042);

diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index c2f5ac0d676e91bda95a9fe22344658444970d73..89b495ece912fcbed997d5e97a0813c3c01c1a95 100644 (file)
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -33,9 +33,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -187,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        wait_all_other_cores_started(bsp_apicid);
 #endif
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index f0ea2acfefae5836d08ff1fca08640c4b7f52a8e..03139d94946b712bcf0914f825e21877fc35fce0 100644 (file)
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -29,10 +29,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 /* UART address and device number */
 #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
 
@@ -201,7 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs780_early_setup();
        sb700_early_setup();
 
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index fb5a6b547445aa9932860905980944887c0a91d1..c3f75e8ce0178341aa266cadbab8ec6ff8e8feb7 100644 (file)
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -1,10 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -171,7 +166,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 
         {
                 msr_t msr;

diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 39f60e006ec21d279187fa723f3593c6060a07f9..d22591095fd1ab320b2d1539a7cd6adeb79b5376 100644 (file)
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -1,10 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -171,7 +166,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 
         {
                 msr_t msr;

diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 39f60e006ec21d279187fa723f3593c6060a07f9..d22591095fd1ab320b2d1539a7cd6adeb79b5376 100644 (file)
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -1,10 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -171,7 +166,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 
         {
                 msr_t msr;

diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index c89893b5cf46aafd56ad991b5bb7005d3a428139..f8c7e11f3783f6c3dbe9463f51e9738dd7f5558d 100644 (file)
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -28,10 +28,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -204,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs780_early_setup();
        sb700_early_setup();
 
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig
index 376518ddb3e24e2eb377cf3619ceda50f46cf7f0..950cb78b1f3be90945d6f9dd96567d0220c0cc7d 100644 (file)
--- a/src/mainboard/kontron/kt690/Kconfig
+++ b/src/mainboard/kontron/kt690/Kconfig
@@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select RAMINIT_SYSINFO
        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index 3f084b36dc246bd6c9fc81c134380707ef71207a..03f81f2485905479f2cb521e3ecdf049c655e505 100644 (file)
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SET_FIDVID 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig
index bd9bbe072b662f60b9d0261c4325f8d4b8c90556..4cfcc1749be13e40242daf787b7c9453ceaf5b7f 100644 (file)
--- a/src/mainboard/msi/ms7260/Kconfig
+++ b/src/mainboard/msi/ms7260/Kconfig
@@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
        select K8_ALLOCATE_IO_RANGE
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 9804518c0d2533a2377bc59639ddc8ff17ea993c..210ea4f8fe82e701b7fe24bd03d37f078a3f08f0 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -28,12 +28,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-/* Used by init_cpus and fidvid. */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -201,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Set up chains and store link pair for optimization later. */
        ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        {
                msr_t msr = rdmsr(0xc0010042);
                print_debug("begin msr fid, vid ");

diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig
index ebae5d137ef01793d76f7448c27c244dfc06d3f8..2d3041ca22fd8dc17276f0979901d5a509b941a3 100644 (file)
--- a/src/mainboard/msi/ms9185/Kconfig
+++ b/src/mainboard/msi/ms9185/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select RAMINIT_SYSINFO
        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index bc6ead6a754b5c728f1c860fbe293453ad3af59e..599a01a37e2ce356d22a5ba6e2351e689bfe5f16 100644 (file)
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -25,11 +25,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -201,7 +196,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 #endif
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 
         {
                 msr_t msr;

diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 942fb1198948d5afd2e37de0f0d98350a6556153..6f24bdccfc104f09f2ceedd12a9d6cd0d09a87f2 100644 (file)
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -24,12 +24,6 @@
 
 #define SET_NB_CFG_54 1
 
-// used by init_cpus and fidvid (disabled until someone tests this)
-// #define SET_FIDVID 1
-#define SET_FIDVID 0
-// if we want to wait for core1 done before DQS training, set it to 0
-// #define SET_FIDVID_CORE0_ONLY 1
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 5ad0719fa70fabd32a1a421d9fdcca6d1c3e0582..18618589c7af5235de720a9a90aacf70943a95a5 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -27,9 +27,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -224,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x38);
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 5cc933d4c0575ce5872838ef512ae4bd9e0092ee..07ab0b0945c498523ba73ad3ce192a258a42887d 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -23,11 +23,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -210,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* it will set up chains and store link pair for optimization later */
        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 
        {
                msr_t msr;

diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig
index 10fcbb368e820ecc2caae63c902a6e3c1abc228b..08151a0ec44ad15f06cce660b1de4462e9988298 100644 (file)
--- a/src/mainboard/supermicro/h8dme/Kconfig
+++ b/src/mainboard/supermicro/h8dme/Kconfig
@@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
        select K8_ALLOCATE_IO_RANGE
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index cb6d8ecddb1e7dad627dfa8b5c8bb088d4a0654f..c1c597bcfcf8a5dbb269e059cadad0c733f84f63 100644 (file)
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -20,11 +20,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-// used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -269,7 +264,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* it will set up chains and store link pair for optimization later */
        ht_setup_chains_x(sysinfo);     // it will init sblnk and sbbusn, nodes, sbdn
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 
        {
                msr_t msr;

diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig
index 5056446328fb76a4de02013a8298bd33e15d7418..77103300b4a8bfd4cbc0c5b827d3aecdd95541bb 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/Kconfig
+++ b/src/mainboard/supermicro/h8dmr/Kconfig
@@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
        select K8_ALLOCATE_IO_RANGE
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 4abb4d099e4bf81e850c7d3e194e2b747fb57ac5..1cf2446c2930bb317c47a10360dfb11e2adca90f 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -23,11 +23,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -198,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);

diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 294677c5c11a09af3c113339fbf6b6e5fffaf609..06347db2abe5cbfdab9698ee9353d0db028942dd 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -27,9 +27,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -214,7 +211,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x38);
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
                msr.hi, msr.lo);

diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index ee858a89cde1c72abe2cc4568af7d08cef31d8a4..5e7b32b4d9162ecd09239ef5e9c00905df11eb44 100644 (file)
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -27,9 +27,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -256,7 +253,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
  post_code(0x38);
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
  msr = rdmsr(0xc0010071);
  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig
index 2efd978d5316d7cac56d4d4847f6855dd65188dd..095f36d67f5c4159e2edd0087dd7a034a37945e3 100644 (file)
--- a/src/mainboard/technexion/tim5690/Kconfig
+++ b/src/mainboard/technexion/tim5690/Kconfig
@@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_512
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 2f61667dbbfe22934375d81882311dbcc0db49ed..f840e087c77c906c71c7c39d744f81b7c82a689d 100644 (file)
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -17,7 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SET_FIDVID 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig
index 953966b8dcc2697065d12c90bd482f95822f5d82..a38d8750507f54c01815a777fbc928f1d97b3cbc 100644 (file)
--- a/src/mainboard/technexion/tim8690/Kconfig
+++ b/src/mainboard/technexion/tim8690/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_512
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string

diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 5426eb4a34b3f1c2f28cad4814c104c5ed8f515f..26738a323e27e8f54a9f41922ffbe1d27b4ce87a 100644 (file)
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -17,7 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SET_FIDVID 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 2f0ef209164c0f36ecc51497c1f820bba98ec1c8..20b6baadbd2e5789c0d193e706cd2000de8d0776 100644 (file)
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -23,11 +23,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
@@ -205,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* it will set up chains and store link pair for optimization later */
        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 
        {
                msr_t msr;

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 61c253bf4711b3bb657d62b874e07a4f4ffaf833..8439740ffbbe79d6b0a9420bbe7ae5c2becd1e39 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -27,9 +27,6 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -216,7 +213,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x38);
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);