add i810 and ich0

[coreboot.git] / util / inteltool / powermgt.c

diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index e985d6b3eb5b19e87c827df9a882b36fb5e61a89..5dd651ba12be4c509875fb96d612cdc3fdf8bbb7 100644 (file)
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -145,6 +145,64 @@ static const io_register_t ich8_pm_registers[] = {
        { 0x7c, 4, "RESERVED" },
 };
 
+static const io_register_t ich0_pm_registers[] = {
+       { 0x00, 2, "PM1_STS" },
+       { 0x02, 2, "PM1_EN" },
+       { 0x04, 4, "PM1_CNT" },
+       { 0x08, 4, "PM1_TMR" },
+       { 0x0c, 4, "RESERVED" },
+       { 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+       /* This register returns 0 on read, but reading it may cause
+        * the system to enter C2 state, which might hang the system.
+        */
+       { 0x14, 1, "LV2" },
+       { 0x15, 1, "RESERVED" },
+       { 0x16, 2, "RESERVED" },
+#endif
+       { 0x18, 4, "RESERVED" },
+       { 0x1c, 4, "RESERVED" },
+       { 0x20, 4, "RESERVED" },
+       { 0x24, 4, "RESERVED" },
+       { 0x28, 4, "GPE0_STS" },
+       { 0x2C, 4, "GPE0_EN" },
+       { 0x30, 2, "SMI_EN" },
+       { 0x32, 2, "RESERVED" },
+       { 0x34, 2, "SMI_STS" },
+       { 0x36, 2, "RESERVED" },
+       { 0x38, 4, "RESERVED" },
+       { 0x3c, 4, "RESERVED" },
+       { 0x40, 2, "IOMON_STS_EN" },
+       { 0x42, 2, "RESERVED" },
+       { 0x44, 2, "DEVACT_STS" },
+       { 0x46, 2, "RESERVED" },
+       { 0x48, 4, "RESERVED" },
+       { 0x4c, 2, "BUS_ADDR_TRACK" },
+       { 0x4e, 1, "BUS_CYC_TRACK" },
+       { 0x4f, 1, "RESERVED" },
+       { 0x50, 4, "RESERVED" },
+       { 0x54, 4, "RESERVED" },
+       { 0x58, 4, "RESERVED" },
+       { 0x5c, 4, "RESERVED" },
+       /* Here start the TCO registers */
+       { 0x60, 1, "TCO_RLD" },
+       { 0x61, 1, "TCO_TMR" },
+       { 0x62, 1, "TCO_DAT_IN" },
+       { 0x63, 1, "TCO_DAT_OUT" },
+       { 0x64, 2, "TCO1_STS" },
+       { 0x66, 2, "TCO2_STS" },
+       { 0x68, 2, "TCO1_CNT" },
+       { 0x6a, 2, "TCO2_CNT" },
+       { 0x6c, 1, "TCO_MESSAGE1" },
+       { 0x6d, 1, "TCO_MESSAGE2" },
+       { 0x6e, 1, "TCO_WDSTATUS" },
+       { 0x6f, 1, "RESERVED" },
+       { 0x70, 4, "RESERVED" },
+       { 0x74, 4, "RESERVED" },
+       { 0x78, 4, "RESERVED" },
+       { 0x7c, 4, "RESERVED" },
+};
+
 int print_pmbase(struct pci_dev *sb)
 {
        int i, size;
@@ -167,6 +225,11 @@ int print_pmbase(struct pci_dev *sb)
                pm_registers = ich8_pm_registers;
                size = ARRAY_SIZE(ich8_pm_registers);
                break;
+       case PCI_DEVICE_ID_INTEL_ICH0:
+               pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+               pm_registers = ich0_pm_registers;
+               size = ARRAY_SIZE(ich0_pm_registers);
+               break;
        case 0x1234: // Dummy for non-existent functionality
                printf("This southbridge does not have PMBASE.\n");
                return 1;