Update AMD F14 Agesa to support Rev C0 cpus

[coreboot.git] / src / vendorcode / amd / agesa / f14 / Proc / GNB / Modules / GnbPcieConfig / PcieConfigData.h

diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
index f40a123a5292840a3ab6428cccf5a8f51ecd1cc6..c3e1cd39a9301889c5bd2ba47372678730fcf8da 100644 (file)
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
@@ -47,6 +47,10 @@
 #ifndef _PCIECONFIGDATA_H_
 #define _PCIECONFIGDATA_H_
 
+AGESA_STATUS
+PcieConfigurationInit (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  );
 
 AGESA_STATUS
 PcieLocateConfigurationData (