Addition of Family12/SB900 wrapper code

[coreboot.git] / src / southbridge / amd / cimx / sb900 / Kconfig

diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
new file mode 100755 (executable)
index 0000000..46f635e
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -0,0 +1,54 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config SOUTHBRIDGE_AMD_CIMX_SB900
+       bool
+       select IOAPIC
+
+if SOUTHBRIDGE_AMD_CIMX_SB900
+config SATA_CONTROLLER_MODE
+       hex
+       default 0x0
+       help
+               0x0 = Native IDE mode.
+               0x1 = RAID mode.
+               0x2 = AHCI mode.
+               0x3 = Legacy IDE mode.
+               0x4 = IDE->AHCI mode.
+               0x5 = AHCI mode as 7804 ID (AMD driver).
+               0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
+
+config PCIB_ENABLE
+       bool
+       default n
+       help
+               n = Disable PCI Bridge Device 14 Function 4.
+               y = Enable PCI Bridge Device 14 Function 4.
+
+config ACPI_SCI_IRQ
+       hex
+       default 0x9
+       help
+               Set SCI IRQ to 9.
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+        string
+        default "southbridge/amd/cimx/sb900/bootblock.c"
+endif #SOUTHBRIDGE_AMD_CIMX_SB900
+