This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / src / northbridge / ibm / cpc710 / cpc710_pci.c

diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.c b/src/northbridge/ibm/cpc710/cpc710_pci.c
index 233e119baf7d4422df6f210dc92a9da37518236b..2b6024e5b9c4eb1eb85d12e869c50fcae10ac08d 100644 (file)
--- a/src/northbridge/ibm/cpc710/cpc710_pci.c
+++ b/src/northbridge/ibm/cpc710/cpc710_pci.c
@@ -45,7 +45,7 @@ cpc710_pci_init(void)
        setCPC710_PCI32(CPC710_PCIL0_MSIZE,  CPC710_PCI32_MEM_SIZE);
        setCPC710_PCI32(CPC710_PCIL0_IOSIZE, CPC710_PCI32_IO_SIZE);
        setCPC710_PCI32(CPC710_PCIL0_SMBAR,  CPC710_PCI32_MEM_BASE);
-       setCPC710_PCI32(CPC710_PCIL0_SIBAR,  CPC710_PCI32_IO_BASE);
+       setCPC710_PCI32(CPC710_PCIL0_SIBAR,  CPC710_PCI32CONFIG_IO_BASE);
        setCPC710_PCI32(CPC710_PCIL0_CTLRW,  0x00000000);
        setCPC710_PCI32(CPC710_PCIL0_PSSIZE, 0x00000080);
        setCPC710_PCI32(CPC710_PCIL0_BARPS,  0x00000000);
@@ -94,7 +94,7 @@ cpc710_pci_init(void)
        setCPC710_PCI64(CPC710_PCIL0_MSIZE,  CPC710_PCI64_MEM_SIZE);
        setCPC710_PCI64(CPC710_PCIL0_IOSIZE, CPC710_PCI64_IO_SIZE);
        setCPC710_PCI64(CPC710_PCIL0_SMBAR,  CPC710_PCI64_MEM_BASE);
-       setCPC710_PCI64(CPC710_PCIL0_SIBAR,  CPC710_PCI64_IO_BASE);
+       setCPC710_PCI64(CPC710_PCIL0_SIBAR,  CPC710_PCI64CONFIG_IO_BASE);
        setCPC710_PCI64(CPC710_PCIL0_CTLRW,  0x02000000);
        setCPC710_PCI64(CPC710_PCIL0_PSSIZE, 0x00000080);