This patch sets max freq defaults for ddr2 and ddr3for fam10.

[coreboot.git] / src / northbridge / amd / amdmct / wrappers / mcti_d.c

diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 569d61c7b03ba572770fc0cebdfc1d4fd1100944..4af75fd0e203a08dcc3761062aa254ed2d5eba21 100644 (file)
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -48,7 +48,7 @@ static u16 mctGet_NVbits(u8 index)
                //val =  200;   /* 200MHz(DDR400) */
                //val =  266;   /* 266MHz(DDR533) */
                //val =  333;   /* 333MHz(DDR667) */
-               val =  400;     /* 400MHz(DDR800) */
+               val =  MEM_MAX_LOAD_FREQ;;      /* 400MHz(DDR800) */
                break;
        case NV_ECC_CAP:
 #if SYSTEM_TYPE == SERVER
@@ -237,7 +237,7 @@ static void mctHookAfterDIMMpre(void)
 
 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 {
-       pDCTstat->PresetmaxFreq = 400;
+       pDCTstat->PresetmaxFreq = MEM_MAX_LOAD_FREQ;
 }
 
 #ifdef UNUSED_CODE